KMAC/UNMASKED Simulation Results

Monday April 14 2025 17:07:51 UTC

GitHub Revision: 24bc68d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	16.060s	2.669ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.750s	28.723us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.840s	75.341us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.040s	12.479ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.930s	95.939us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.190s	145.643us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.840s	75.341us	1	1	100.00
		kmac_csr_aliasing	3.930s	95.939us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.760s	36.599us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.140s	70.601us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	8.092m	54.252ms	1	1	100.00
V2	burst_write	kmac_burst_write	12.030m	33.560ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.689m	253.063ms	1	1	100.00
		kmac_test_vectors_sha3_256	18.601m	17.023ms	1	1	100.00
		kmac_test_vectors_sha3_384	17.120s	5.050ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.374m	132.614ms	1	1	100.00
		kmac_test_vectors_shake_128	1.668m	10.823ms	1	1	100.00
		kmac_test_vectors_shake_256	1.450m	4.939ms	1	1	100.00
		kmac_test_vectors_kmac	3.310s	104.865us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.960s	114.793us	1	1	100.00
V2	sideload	kmac_sideload	3.600m	4.597ms	1	1	100.00
V2	app	kmac_app	3.430s	40.832us	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	34.290s	7.267ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	28.210s	6.587ms	1	1	100.00
V2	error	kmac_error	3.752m	9.158ms	1	1	100.00
V2	key_error	kmac_key_error	9.480s	5.459ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.010s	59.476us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	28.780s	6.368ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	6.270s	657.060us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	16.760s	5.411ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.270s	76.470us	1	1	100.00
V2	stress_all	kmac_stress_all	1.284m	2.519ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.610s	28.933us	1	1	100.00
V2	alert_test	kmac_alert_test	2.010s	46.394us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.470s	250.331us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.470s	250.331us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.750s	28.723us	1	1	100.00
		kmac_csr_rw	1.840s	75.341us	1	1	100.00
		kmac_csr_aliasing	3.930s	95.939us	1	1	100.00
		kmac_same_csr_outstanding	2.240s	185.968us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.750s	28.723us	1	1	100.00
		kmac_csr_rw	1.840s	75.341us	1	1	100.00
		kmac_csr_aliasing	3.930s	95.939us	1	1	100.00
		kmac_same_csr_outstanding	2.240s	185.968us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.280s	141.999us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.280s	141.999us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.280s	141.999us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.280s	141.999us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.760s	6.414us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	51.000s	10.445ms	1	1	100.00
		kmac_tl_intg_err	2.620s	137.275us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.620s	137.275us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.270s	76.470us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	16.060s	2.669ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.600m	4.597ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.280s	141.999us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	51.000s	10.445ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	51.000s	10.445ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	51.000s	10.445ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	16.060s	2.669ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.270s	76.470us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	51.000s	10.445ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.468m	3.620ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	16.060s	2.669ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.038m	9.904ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.71843867152551952124198472076644578790751128881714252246453225079336962270281
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
        UVM_ERROR @   6414321 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
        UVM_INFO @   6414321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---