ROM_CTRL/32KB Simulation Results

Monday April 14 2025 17:07:51 UTC

GitHub Revision: 24bc68d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.670s 432.018us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.500s 202.069us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.970s 170.207us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.370s 726.950us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.220s 214.028us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.910s 170.827us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.970s 170.207us 1 1 100.00
rom_ctrl_csr_aliasing 4.220s 214.028us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.620s 206.206us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.140s 170.400us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.180s 744.889us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 10.080s 1.219ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 8.520s 300.330us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 3.720s 386.021us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 5.560s 677.847us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 5.560s 677.847us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.500s 202.069us 1 1 100.00
rom_ctrl_csr_rw 4.970s 170.207us 1 1 100.00
rom_ctrl_csr_aliasing 4.220s 214.028us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.810s 182.017us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.500s 202.069us 1 1 100.00
rom_ctrl_csr_rw 4.970s 170.207us 1 1 100.00
rom_ctrl_csr_aliasing 4.220s 214.028us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.810s 182.017us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 55.300s 6.406ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 13.850s 2.223ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.578m 1.320ms 1 1 100.00
rom_ctrl_tl_intg_err 21.670s 421.949us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.578m 1.320ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.578m 1.320ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 55.300s 6.406ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 55.300s 6.406ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 55.300s 6.406ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 55.300s 6.406ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 55.300s 6.406ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.578m 1.320ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.578m 1.320ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.670s 432.018us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.670s 432.018us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.670s 432.018us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 21.670s 421.949us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 55.300s 6.406ms 1 1 100.00
rom_ctrl_kmac_err_chk 8.520s 300.330us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 55.300s 6.406ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 55.300s 6.406ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 55.300s 6.406ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 13.850s 2.223ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.578m 1.320ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 54.690s 12.283ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00