ROM_CTRL/64KB Simulation Results

Monday April 14 2025 17:07:51 UTC

GitHub Revision: 24bc68d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.230s 582.030us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.280s 737.080us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.650s 730.336us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.600s 729.572us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.770s 301.698us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.250s 1.286ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.650s 730.336us 1 1 100.00
rom_ctrl_csr_aliasing 7.770s 301.698us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.680s 400.639us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.100s 206.663us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.940s 1.200ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 21.710s 3.571ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.450s 544.867us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.090s 212.296us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.740s 954.976us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.740s 954.976us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.280s 737.080us 1 1 100.00
rom_ctrl_csr_rw 5.650s 730.336us 1 1 100.00
rom_ctrl_csr_aliasing 7.770s 301.698us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.540s 296.175us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.280s 737.080us 1 1 100.00
rom_ctrl_csr_rw 5.650s 730.336us 1 1 100.00
rom_ctrl_csr_aliasing 7.770s 301.698us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.540s 296.175us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.793m 9.720ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 25.830s 1.101ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.533m 709.851us 1 1 100.00
rom_ctrl_tl_intg_err 37.720s 482.796us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.533m 709.851us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.533m 709.851us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.793m 9.720ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.793m 9.720ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.793m 9.720ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.793m 9.720ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.793m 9.720ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.533m 709.851us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.533m 709.851us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.230s 582.030us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.230s 582.030us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.230s 582.030us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 37.720s 482.796us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.793m 9.720ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.450s 544.867us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.793m 9.720ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.793m 9.720ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.793m 9.720ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 25.830s 1.101ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.533m 709.851us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 10.610s 381.091us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00