SPI_DEVICE/1R1W Simulation Results

Monday April 14 2025 17:07:51 UTC

GitHub Revision: 24bc68d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.360m	13.060ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.010s	32.746us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.910s	34.907us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	26.900s	2.834ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.130s	975.857us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.150s	360.818us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.910s	34.907us	1	1	100.00
		spi_device_csr_aliasing	11.130s	975.857us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.540s	38.310us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.370s	78.098us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.720s	65.329us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.680s	1.392us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.610s	2.682us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.400s	90.600us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.400s	90.600us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	9.640s	4.045ms	1	1	100.00
		spi_device_tpm_sts_read	1.770s	18.875us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	9.380s	9.608ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	13.040s	10.769ms	1	1	100.00
		spi_device_flash_all	1.103m	84.919ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.120s	277.984us	1	1	100.00
		spi_device_flash_all	1.103m	84.919ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.120s	277.984us	1	1	100.00
		spi_device_flash_all	1.103m	84.919ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.103m	84.919ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.440s	243.090us	1	1	100.00
		spi_device_flash_all	1.103m	84.919ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.440s	243.090us	1	1	100.00
		spi_device_flash_all	1.103m	84.919ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.440s	243.090us	1	1	100.00
		spi_device_flash_all	1.103m	84.919ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.440s	243.090us	1	1	100.00
		spi_device_flash_all	1.103m	84.919ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.440s	243.090us	1	1	100.00
		spi_device_flash_all	1.103m	84.919ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	6.420s	3.688ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	3.270s	56.715us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.270s	56.715us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.270s	56.715us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.090s	1.047ms	1	1	100.00
		spi_device_read_buffer_direct	3.970s	1.528ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.270s	56.715us	1	1	100.00
		spi_device_flash_all	1.103m	84.919ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.103m	84.919ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.103m	84.919ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.250s	112.432us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.250s	112.432us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.360m	13.060ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	3.436m	138.796ms	1	1	100.00
V2	stress_all	spi_device_stress_all	7.314m	137.607ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.560s	32.613us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.620s	48.945us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.570s	228.613us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.570s	228.613us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.010s	32.746us	1	1	100.00
		spi_device_csr_rw	1.910s	34.907us	1	1	100.00
		spi_device_csr_aliasing	11.130s	975.857us	1	1	100.00
		spi_device_same_csr_outstanding	2.400s	153.795us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.010s	32.746us	1	1	100.00
		spi_device_csr_rw	1.910s	34.907us	1	1	100.00
		spi_device_csr_aliasing	11.130s	975.857us	1	1	100.00
		spi_device_same_csr_outstanding	2.400s	153.795us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.170s	285.980us	1	1	100.00
		spi_device_tl_intg_err	16.400s	1.070ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.400s	1.070ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.753m	80.828ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.17482782014116869814295431480794264295700399108175087270299822208121211925179
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    912164 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[24])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    912164 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    912164 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[920])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.18957661405306859861070345234430581665934178546882608200049485875396809485553
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2017112 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2017112 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   2076112 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd0e4e6 [110100001110010011100110] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   2076112 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0xd0e4e6 [110100001110010011100110] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])