SPI_HOST Simulation Results

Monday April 14 2025 17:07:51 UTC

GitHub Revision: 24bc68d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.533m	2.698ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	35.654us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	38.361us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	49.245us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	97.458us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	54.901us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	38.361us	1	1	100.00
		spi_host_csr_aliasing	4.000s	97.458us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	22.808us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	180.487us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	14.000s	445.825us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	8.000s	81.655us	1	1	100.00
		spi_host_error_cmd	5.000s	19.937us	1	1	100.00
		spi_host_event	12.000s	3.738ms	1	1	100.00
V2	clock_rate	spi_host_speed	16.000s	382.602us	1	1	100.00
V2	speed	spi_host_speed	16.000s	382.602us	1	1	100.00
V2	chip_select_timing	spi_host_speed	16.000s	382.602us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	11.000s	187.123us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	168.126us	1	1	100.00
V2	cpol_cpha	spi_host_speed	16.000s	382.602us	1	1	100.00
V2	full_cycle	spi_host_speed	16.000s	382.602us	1	1	100.00
V2	duplex	spi_host_smoke	1.533m	2.698ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	1.533m	2.698ms	1	1	100.00
V2	stress_all	spi_host_stress_all	28.000s	5.402ms	1	1	100.00
V2	spien	spi_host_spien	7.000s	316.478us	1	1	100.00
V2	stall	spi_host_status_stall	2.167m	53.222ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	320.473us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	8.000s	81.655us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	45.669us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	25.915us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	30.101us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	30.101us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	35.654us	1	1	100.00
		spi_host_csr_rw	4.000s	38.361us	1	1	100.00
		spi_host_csr_aliasing	4.000s	97.458us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	56.282us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	35.654us	1	1	100.00
		spi_host_csr_rw	4.000s	38.361us	1	1	100.00
		spi_host_csr_aliasing	4.000s	97.458us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	56.282us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	332.743us	1	1	100.00
		spi_host_sec_cm	4.000s	68.199us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	332.743us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	52.250m	164.721ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.82099752192872678707160272296150256652768040949935111368833599275360589020749
      Line 157, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 164721201446 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xeaa53654, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
        UVM_INFO @ 164721201446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---