SRAM_CTRL/MAIN Simulation Results

Monday April 14 2025 17:07:51 UTC

GitHub Revision: 24bc68d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	4.020s	730.560us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.830s	52.850us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.530s	39.741us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.150s	45.258us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.730s	69.668us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.210s	616.088us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.530s	39.741us	1	1	100.00
		sram_ctrl_csr_aliasing	1.730s	69.668us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.034m	17.937ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.015m	7.073ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.971m	119.571ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.545m	57.592ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	15.236m	40.117ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	12.644m	35.881ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	46.960s	13.354ms	1	1	100.00
V2	executable	sram_ctrl_executable	14.129m	136.578ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	8.080s	1.503ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.605m	17.560ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	5.480s	695.219us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	48.930s	3.130ms	1	1	100.00
		sram_ctrl_throughput_w_readback	12.950s	1.538ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.705m	65.224ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.370s	353.151us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	40.401m	400.252ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.630s	31.169us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.000s	38.633us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.000s	38.633us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.830s	52.850us	1	1	100.00
		sram_ctrl_csr_rw	1.530s	39.741us	1	1	100.00
		sram_ctrl_csr_aliasing	1.730s	69.668us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.780s	40.856us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.830s	52.850us	1	1	100.00
		sram_ctrl_csr_rw	1.530s	39.741us	1	1	100.00
		sram_ctrl_csr_aliasing	1.730s	69.668us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.780s	40.856us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	34.980s	30.623ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.510s	2.160us	0	1	0.00
		sram_ctrl_tl_intg_err	2.160s	94.905us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.510s	2.160us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.160s	94.905us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.705m	65.224ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.705m	65.224ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.530s	39.741us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	14.129m	136.578ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	14.129m	136.578ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	14.129m	136.578ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	46.960s	13.354ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.720s	1.832ms	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	34.980s	30.623ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.720s	3.296ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	4.020s	730.560us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	4.020s	730.560us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	14.129m	136.578ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.510s	2.160us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	46.960s	13.354ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.510s	2.160us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.510s	2.160us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	4.020s	730.560us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.510s	2.160us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	15.350s	855.047us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.70106352141878950861284501598114664837732363346162300036121305193218825110746
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 1832302252 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 1832302252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.10741446475168615179795083684866786193007979339131050156000534529301950480294
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   2159641 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   2159641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---