SRAM_CTRL/RET Simulation Results

Monday April 14 2025 17:07:51 UTC

GitHub Revision: 24bc68d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	16.910s	2.967ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.770s	14.210us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.470s	34.615us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.550s	83.519us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.670s	15.624us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.410s	67.965us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.470s	34.615us	1	1	100.00
		sram_ctrl_csr_aliasing	1.670s	15.624us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.110s	340.239us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.250s	161.924us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.869m	1.869ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.351m	3.978ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	13.930s	1.102ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	9.304m	3.515ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.950s	185.588us	1	1	100.00
V2	executable	sram_ctrl_executable	9.059m	3.717ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	10.050s	2.464ms	1	1	100.00
		sram_ctrl_partial_access_b2b	2.434m	10.692ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	31.500s	106.694us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	9.900s	319.147us	1	1	100.00
		sram_ctrl_throughput_w_readback	19.680s	1.060ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	54.570s	6.890ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.690s	86.833us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	28.165m	50.068ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.610s	12.007us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.000s	261.914us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.000s	261.914us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.770s	14.210us	1	1	100.00
		sram_ctrl_csr_rw	1.470s	34.615us	1	1	100.00
		sram_ctrl_csr_aliasing	1.670s	15.624us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.690s	49.719us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.770s	14.210us	1	1	100.00
		sram_ctrl_csr_rw	1.470s	34.615us	1	1	100.00
		sram_ctrl_csr_aliasing	1.670s	15.624us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.690s	49.719us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.110s	773.131us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.620s	5.209us	0	1	0.00
		sram_ctrl_tl_intg_err	2.390s	233.721us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.620s	5.209us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.390s	233.721us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	54.570s	6.890ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	54.570s	6.890ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.470s	34.615us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	9.059m	3.717ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	9.059m	3.717ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	9.059m	3.717ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.950s	185.588us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.790s	38.087us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.110s	773.131us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.870s	46.848us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	16.910s	2.967ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	16.910s	2.967ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	9.059m	3.717ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.620s	5.209us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.950s	185.588us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.620s	5.209us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.620s	5.209us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	16.910s	2.967ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.620s	5.209us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.494m	7.608ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.79981942663351206805926800020578800478623701395959803747070132740503555026821
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  46847883 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x10) != exp (0x32)
        UVM_INFO @  46847883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.110319566933123261465151154073974839557539875478319609837509456201887410571552
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   5209101 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   5209101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---