UART Simulation Results

Monday April 14 2025 17:07:51 UTC

GitHub Revision: 24bc68d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	3.710s	979.478us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.410s	25.255us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.520s	36.557us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.980s	370.663us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.630s	19.300us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.590s	16.145us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.520s	36.557us	1	1	100.00
		uart_csr_aliasing	1.630s	19.300us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	53.170s	50.587ms	1	1	100.00
V2	parity	uart_smoke	3.710s	979.478us	1	1	100.00
		uart_tx_rx	53.170s	50.587ms	1	1	100.00
V2	parity_error	uart_intr	2.402m	704.238ms	1	1	100.00
		uart_rx_parity_err	29.250s	96.960ms	1	1	100.00
V2	watermark	uart_tx_rx	53.170s	50.587ms	1	1	100.00
		uart_intr	2.402m	704.238ms	1	1	100.00
V2	fifo_full	uart_fifo_full	56.740s	32.212ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	33.210s	17.520ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	17.100s	44.524ms	1	1	100.00
V2	rx_frame_err	uart_intr	2.402m	704.238ms	1	1	100.00
V2	rx_break_err	uart_intr	2.402m	704.238ms	1	1	100.00
V2	rx_timeout	uart_intr	2.402m	704.238ms	1	1	100.00
V2	perf	uart_perf	1.131m	3.836ms	1	1	100.00
V2	sys_loopback	uart_loopback	7.360s	5.091ms	1	1	100.00
V2	line_loopback	uart_loopback	7.360s	5.091ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	50.730s	40.496ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	26.500s	23.662ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.950s	1.309ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	23.350s	4.341ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.010m	66.761ms	1	1	100.00
V2	stress_all	uart_stress_all	8.695m	186.792ms	1	1	100.00
V2	alert_test	uart_alert_test	1.480s	14.479us	1	1	100.00
V2	intr_test	uart_intr_test	1.560s	14.462us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.450s	113.334us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.450s	113.334us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.410s	25.255us	1	1	100.00
		uart_csr_rw	1.520s	36.557us	1	1	100.00
		uart_csr_aliasing	1.630s	19.300us	1	1	100.00
		uart_same_csr_outstanding	1.710s	29.099us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.410s	25.255us	1	1	100.00
		uart_csr_rw	1.520s	36.557us	1	1	100.00
		uart_csr_aliasing	1.630s	19.300us	1	1	100.00
		uart_same_csr_outstanding	1.710s	29.099us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.830s	59.269us	1	1	100.00
		uart_tl_intg_err	2.050s	286.547us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.050s	286.547us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	39.580s	1.609ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00