CHIP Simulation Results

Monday April 14 2025 17:07:51 UTC

GitHub Revision: `24bc68d`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.154m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.154m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	12.539s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	13.897s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	12.479s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.614m	4.819ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.614m	4.819ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.614m	4.819ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	2.701m		0	1	0.00
		chip_sw_example_manufacturer	2.794m		0	1	0.00
		chip_sw_example_concurrency	4.045m	3.110ms	1	1	100.00
		chip_sw_uart_smoketest_signed	10.961s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	9.440s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	10.220s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	10.220s		0	1	0.00
V1	xbar_smoke	xbar_smoke	18.630s	57.418us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.745m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.918m	10.560ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.517m	4.202ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	11.835s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	10.860s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	12.182s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	11.813s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.590s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.590s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.070m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.009m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.561m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.561m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.361m	4.174ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.064m	4.012ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.350m	9.594ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.726s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.411s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	8.285m	18.431ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.067m	4.955ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	20.785m	18.023ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	20.785m	18.023ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.596s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.617s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.617s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	11.489s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.002m	4.209ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.905m	5.485ms	1	1	100.00
		chip_sw_aes_idle	3.684m	4.988ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.683m	5.315ms	1	1	100.00
		chip_sw_kmac_idle	3.703m	5.892ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.341s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.349s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.551s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.537s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	13.524s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.163s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.146s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.961s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.757s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.949s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.372s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	13.524s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.163s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.146s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.961s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.757s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.949s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.372s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.619s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.195m	10.180us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	47.210s	10.140us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	46.650s	10.340us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	51.770s	10.100us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.656s		0	1	0.00
		chip_sw_clkmgr_jitter	3.293m	4.525ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.627m	4.809ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	11.727s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	46.810s	10.260us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	46.120s	10.220us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1.024m	10.400us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	48.120s	10.280us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	46.310s	10.320us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.153s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.924s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.594s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	10.653s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	18.692m	17.493ms	0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.634m	14.526ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	10.617s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.623s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.634m	14.526ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	18.591s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	11.880s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	13.065s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	16.059s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.560s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	18.692m	17.493ms	0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.350m	9.594ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	25.666m	20.018ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.235m	12.018ms	0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	10.935m	30.016ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.778m	4.936ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	18.692m	17.493ms	0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.268s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.723s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	18.692m	17.493ms	0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	10.708s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	10.935m	30.016ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.435s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.097s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.245s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.939s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.002s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.511s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.723s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	13.831s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	14.386s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	13.831s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	13.831s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	13.831s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.399m	8.668ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	16.021s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	11.856s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	17.648s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	16.485s		0	1	0.00
		chip_sw_lc_ctrl_transition	13.831s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.505m	8.115ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.339m	11.384ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.192s		0	1	0.00
		chip_prim_tl_access	7.768m	12.437ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	13.524s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.163s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.146s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.961s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.757s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.949s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.372s		0	1	0.00
		chip_rv_dm_lc_disabled	8.285m	18.431ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.333m	3.725ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.195m	10.180us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.022m	4.695ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.684m	4.988ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.682m	4.478ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	47.210s	10.140us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.683m	5.315ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.052m	3.979ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.199m	3.722ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	51.770s	10.100us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.505m	8.115ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	13.831s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	50.010s	10.400us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.600m	6.551ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.703m	5.892ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.144s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.144s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.594s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.638m	5.786ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.796s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.505m	8.115ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	46.650s	10.340us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	11.254s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	12.619s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.905m	5.485ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.905m	5.485ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.905m	5.485ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	6.985m	5.848ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.339m	11.384ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.339m	11.384ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.327m	7.056ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.656s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.192s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	18.692m	17.493ms	0	1	0.00
		chip_sw_data_integrity_escalation	2.561m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	13.831s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	6.985m	5.848ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.505m	8.115ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.327m	7.056ms	0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	3.783m	5.495ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	6.985m	5.848ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.505m	8.115ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.327m	7.056ms	0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	3.783m	5.495ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	13.831s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	13.658s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	14.386s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	16.021s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	11.856s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	17.648s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	16.485s		0	1	0.00
		chip_sw_lc_ctrl_transition	13.831s		0	1	0.00
		chip_prim_tl_access	7.768m	12.437ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	7.768m	12.437ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	15.930s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.753s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.924s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.619s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.195m	10.180us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	47.210s	10.140us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	46.650s	10.340us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	51.770s	10.100us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.656s		0	1	0.00
		chip_sw_clkmgr_jitter	3.293m	4.525ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	6.846m	9.954ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	6.846m	9.954ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.876m	5.930ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.441m	3.954ms	1	1	100.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.744m	5.037ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.644m	6.381ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.641m	4.851ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.177m	5.790ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.783m	5.495ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	25.666m	20.018ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	25.666m	20.018ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.556m	3.435ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.481m	4.524ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.934m	4.679ms	1	1	100.00
		chip_sw_csrng_smoketest	2.975m	3.615ms	1	1	100.00
		chip_sw_gpio_smoketest	3.196m	4.128ms	1	1	100.00
		chip_sw_hmac_smoketest	4.000m	4.024ms	1	1	100.00
		chip_sw_kmac_smoketest	3.659m	4.670ms	1	1	100.00
		chip_sw_otbn_smoketest	4.349m	5.119ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.191m	4.242ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.638m	5.798ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.077m	4.642ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.093m	5.689ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.298m	3.306ms	1	1	100.00
		chip_sw_uart_smoketest	3.092m	4.860ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	29.085s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	10.961s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.745m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	11.642s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	5.090m	3.865ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.455m	5.739ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.937m	6.593ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.502m	3.821ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	10.667s		0	1	0.00
		chip_rv_dm_lc_disabled	8.285m	18.431ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.537s		0	1	0.00
		chip_sw_lc_walkthrough_prod	12.340s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	11.439s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.461s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	10.667s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	12.763s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	13.002s		0	1	0.00
		rom_volatile_raw_unlock	11.053s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.452s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	13.320s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.184m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.405m	5.382ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.405m	5.382ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	10.220s		0	1	0.00
		chip_same_csr_outstanding	9.330s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	10.220s		0	1	0.00
		chip_same_csr_outstanding	9.330s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	45.600s	41.145us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.950s	13.012us	1	1	100.00
		xbar_smoke_large_delays	4.631m	2.395ms	1	1	100.00
		xbar_smoke_slow_rsp	4.883m	1.852ms	1	1	100.00
		xbar_random_zero_delays	51.110s	52.792us	1	1	100.00
		xbar_random_large_delays	17.013m	8.680ms	1	1	100.00
		xbar_random_slow_rsp	17.991m	6.512ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	16.600s	31.597us	1	1	100.00
		xbar_error_and_unmapped_addr	1.342m	197.327us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	31.060s	30.074us	1	1	100.00
		xbar_error_and_unmapped_addr	1.342m	197.327us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	4.826m	793.991us	1	1	100.00
		xbar_access_same_device_slow_rsp	30.538m	11.758ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.752m	328.011us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	15.146m	2.163ms	1	1	100.00
		xbar_stress_all_with_error	11.538m	2.141ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	29.201m	2.977ms	1	1	100.00
		xbar_stress_all_with_reset_error	56.500s	71.457us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	11.075s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	13.040s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	10.914s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.724s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.553s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.498s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.354s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.909s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.772s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	12.320s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.583s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.927s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.140s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.678s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.854s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.387s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.820s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.516s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.132s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.951s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.748s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.731s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.976s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.826s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.597s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.567s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.620s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.620s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.741s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.739s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.117s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.589s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.973s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.988s		0	1	0.00
		rom_e2e_asm_init_dev	11.509s		0	1	0.00
		rom_e2e_asm_init_prod	11.908s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.015s		0	1	0.00
		rom_e2e_asm_init_rma	10.932s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.616s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.640s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.241s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.026s		0	1	0.00
V2		TOTAL			64	205	31.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.729m	3.792ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.903m	4.871ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.004s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.725s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.730s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.355s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	18.692m	17.493ms	0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	11.953s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.092m	17.603ms	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	10.563s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	10.383s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.004s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.725s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.730s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.976s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.577s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.717s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.198m		0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	20.046m	16.491ms	1	1	100.00
		chip_plic_all_irqs_0	8.970m	7.057ms	1	1	100.00
		chip_plic_all_irqs_10	9.692m	6.457ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.176m	4.935ms	1	1	100.00
		chip_sw_dma_abort	4.528m	4.887ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.945s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.547s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.249s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.096s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.315s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.587s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.037s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.722s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.849s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.410s		0	1	0.00
		chip_sw_mbx_smoketest	4.461m	4.949ms	1	1	100.00
		TOTAL			74	247	29.96

Failure Buckets

Job returned non-zero exit code has 143 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.19561481222526646608271573288155804054012061651770869474368022359819908246393
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  DEBUG: /nightly/runs/opentitan/rules/autogen.bzl:452:14: NOTE: stamping is disabled, the chip_info section will use a fixed version string
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (f31a40)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (5733d4)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 143.701s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.32187488143187876748540475060742685001533282454369838099465374026655345397445
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (9b7d61)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 150.685s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.77036588579795183676027934420400208514051172802454215808854322919014338093086
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (5d89aa)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 142.730s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.80862235989643311344185864561283300658134836538536455156082263222996781111130
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (c492f2)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 112.823s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.53486383634085534587814351097562227354251990642079119461223541464560132436053
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (376831)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 109.666s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 138 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.44027020449771900183518978641640920843040714824647304279689005856988948380440
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.63112197551495417260333110632250025154815349005757147595806049065088213409328
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.80920835096839835297807838993199382722793179484558864722446330930549874958700
    Line 406, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.4528602496911069261541535204881389741640725600788239300924894026212420887676
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.99416150196690848620470539879581196034680049304213588250137343227487139046703
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_rstmgr_sw_req has 1 failures.

0.chip_sw_rstmgr_sw_req.47042172740678091202023938770649077723185833319108080878577061090357668811549
Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest/run.log

  UVM_ERROR @ 12017.853442 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12017.853442 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_alert_info has 1 failures.

0.chip_sw_rstmgr_alert_info.101337320691411298689804814170761288084726975033972029891312448227630094125209
Line 443, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30015.673414 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30015.673414 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.88566312422759381439351971914862211291615572453652776106706584740712936157057
Line 458, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20017.794085 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20017.794085 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.1816931230209887044940808302226043935120970733484278561703078871968572056469
Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18023.061337 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18023.061337 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.74320207817306302043690338304530994120993962491960780618930181656582545524475
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.78303982537724007131721059180038655081844447339834608242300871736034715271846
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.4879324655114685903043001766213739179408233746255149570866430242227000440521
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.104120169616994976823804399958838163312943656295999703024448545973032776898061
Line 467, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8115.134160 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (86010303678884353154760243439111536343425070963265697677524237814762980519629 [0xbe281b524838392c8d8ec2e420512847440f1afa2ba6cf45806fad46f49c2ecd] vs 25074262276174612192717466987651172466620018722383239917273796642461226312218 [0x376f878e965d85c81b9e61c824fcaf24b3741a260fb048146bb6db89de27221a])
  UVM_INFO @ 8115.134160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.34202251427783687371104297593148748522629587672038204593734837857505518008151
Line 459, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 8668.483960 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (86852851997817511128372394573607945261029981752944853503826301058381375185867 [0xc004f8e059b9b790a1f0e0f705b9605d8008cd44f04553c038b12d92308da3cb] vs 92665334106934113415719229616686827417331604982500922282629007256184581490027 [0xccdeb8703fdbe457aa17f68955e8bedae7c4bc86a52e28b7c35ce9fc1f5b856b])
  UVM_INFO @ 8668.483960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.44207841533573428564779111289766008136240880343830163463888730984302996619288
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4173.788859 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h7a49a7  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h1  a_user: 'h248ea  d_param: 'h0  d_source: 'h39  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4173.788859 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.49964265642367281238585374900567882450646387785567693164399712198848905601342
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4012.402689 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h26b0cf14  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h0  a_user: 'h26964  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4012.402689 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.109646732491972582964315710370622764682044674933439853194706113155316358336058
    Line 446, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 17492.652484 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 17492.652484 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.62826247089585165508073776312268025382462464209907100047325258337283907035434
    Line 447, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4202.163028 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4202.163028 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_otp_ctrl_escalation_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.48868010349792592313350703752691803908362961885908897844633331943835597217128
    Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
  UVM_ERROR @ 17603.452064 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_escalation_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 17603.452064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.47127707804730452165724476491398688651683952111237880474651561215239676734812
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5929.968376 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5929.968376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.48601771141036446451565400473768369499116341724854321070554852904858182647667
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6380.984600 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6380.984600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.27924670361123433133414851572983882856842258743394713468366723934865656757393
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_sram_ctrl_scrambled_access has 1 failures.
  - 0.chip_sw_sram_ctrl_scrambled_access.47154469411043675897567397882583818889651539655177421178215377012661656506569
    Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access/latest/run.log
```
  UVM_ERROR @ 7055.808476 us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 7055.808476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@35844) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.6153724111828358607225016165928655232639289366107623494871933640918480331024
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 5382.466296 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@35844) { a_addr: 'h2210  a_data: 'h6d6cf726  a_mask: 'h9  a_size: 'h2  a_param: 'h0  a_source: 'hf6  a_opcode: 'h4  a_user: 'h2711e  d_param: 'h0  d_source: 'hf6  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5382.466296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.2259323489577802333051994550554108499012969458864555145228160904506328244930
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.6279849522179761256108804331200122511803041919310579589968944798550054724274
    Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4887.041160 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4887.041160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```