DMA Simulation Results

Tuesday April 15 2025 17:03:28 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	306.308us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	303.509us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	303.614us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	29.204us	1	1	100.00
V1	csr_rw	dma_csr_rw	5.000s	46.878us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	10.000s	678.717us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	78.739us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	46.457us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	5.000s	46.878us	1	1	100.00
		dma_csr_aliasing	6.000s	78.739us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	49.000s	3.591ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	34.417m	221.863ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	1.283m	5.921ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	33.983m	1.057s	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	34.417m	221.863ms	1	1	100.00
V2	dma_abort	dma_abort	11.000s	6.463ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.617m	32.947ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	58.738us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	161.177us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	161.177us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	29.204us	1	1	100.00
		dma_csr_rw	5.000s	46.878us	1	1	100.00
		dma_csr_aliasing	6.000s	78.739us	1	1	100.00
		dma_same_csr_outstanding	4.000s	39.219us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	29.204us	1	1	100.00
		dma_csr_rw	5.000s	46.878us	1	1	100.00
		dma_csr_aliasing	6.000s	78.739us	1	1	100.00
		dma_same_csr_outstanding	4.000s	39.219us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	18.000s	218.717us	1	1	100.00
		dma_generic_stress	33.983m	1.057s	1	1	100.00
		dma_handshake_stress	34.417m	221.863ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	112.383us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.800m	53.377ms	1	1	100.00
		dma_longer_transfer	5.000s	145.192us	1	1	100.00
		TOTAL			21	21	100.00