HMAC Simulation Results

Tuesday April 15 2025 17:03:28 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 11.710s 4.476ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.770s 42.092us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.670s 34.836us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 10.600s 312.514us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.250s 162.306us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.600s 22.163us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.670s 34.836us 1 1 100.00
hmac_csr_aliasing 3.250s 162.306us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 26.010s 8.216ms 1 1 100.00
V2 back_pressure hmac_back_pressure 35.610s 842.103us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 9.010s 171.607us 1 1 100.00
hmac_test_sha384_vectors 27.100s 436.248us 1 1 100.00
hmac_test_sha512_vectors 22.530s 216.868us 1 1 100.00
hmac_test_hmac256_vectors 8.250s 2.473ms 1 1 100.00
hmac_test_hmac384_vectors 8.170s 266.683us 1 1 100.00
hmac_test_hmac512_vectors 13.540s 882.820us 1 1 100.00
V2 burst_wr hmac_burst_wr 8.510s 204.219us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 6.270m 4.060ms 1 1 100.00
V2 error hmac_error 36.060s 1.805ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 39.790s 3.368ms 1 1 100.00
V2 save_and_restore hmac_smoke 11.710s 4.476ms 1 1 100.00
hmac_long_msg 26.010s 8.216ms 1 1 100.00
hmac_back_pressure 35.610s 842.103us 1 1 100.00
hmac_datapath_stress 6.270m 4.060ms 1 1 100.00
hmac_burst_wr 8.510s 204.219us 1 1 100.00
hmac_stress_all 6.631m 160.265ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 11.710s 4.476ms 1 1 100.00
hmac_long_msg 26.010s 8.216ms 1 1 100.00
hmac_back_pressure 35.610s 842.103us 1 1 100.00
hmac_datapath_stress 6.270m 4.060ms 1 1 100.00
hmac_wipe_secret 39.790s 3.368ms 1 1 100.00
hmac_test_sha256_vectors 9.010s 171.607us 1 1 100.00
hmac_test_sha384_vectors 27.100s 436.248us 1 1 100.00
hmac_test_sha512_vectors 22.530s 216.868us 1 1 100.00
hmac_test_hmac256_vectors 8.250s 2.473ms 1 1 100.00
hmac_test_hmac384_vectors 8.170s 266.683us 1 1 100.00
hmac_test_hmac512_vectors 13.540s 882.820us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 11.710s 4.476ms 1 1 100.00
hmac_long_msg 26.010s 8.216ms 1 1 100.00
hmac_back_pressure 35.610s 842.103us 1 1 100.00
hmac_datapath_stress 6.270m 4.060ms 1 1 100.00
hmac_burst_wr 8.510s 204.219us 1 1 100.00
hmac_error 36.060s 1.805ms 1 1 100.00
hmac_wipe_secret 39.790s 3.368ms 1 1 100.00
hmac_test_sha256_vectors 9.010s 171.607us 1 1 100.00
hmac_test_sha384_vectors 27.100s 436.248us 1 1 100.00
hmac_test_sha512_vectors 22.530s 216.868us 1 1 100.00
hmac_test_hmac256_vectors 8.250s 2.473ms 1 1 100.00
hmac_test_hmac384_vectors 8.170s 266.683us 1 1 100.00
hmac_test_hmac512_vectors 13.540s 882.820us 1 1 100.00
hmac_stress_all 6.631m 160.265ms 1 1 100.00
V2 stress_all hmac_stress_all 6.631m 160.265ms 1 1 100.00
V2 alert_test hmac_alert_test 1.570s 14.703us 1 1 100.00
V2 intr_test hmac_intr_test 1.400s 39.560us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.480s 282.149us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.480s 282.149us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.770s 42.092us 1 1 100.00
hmac_csr_rw 1.670s 34.836us 1 1 100.00
hmac_csr_aliasing 3.250s 162.306us 1 1 100.00
hmac_same_csr_outstanding 2.470s 74.106us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.770s 42.092us 1 1 100.00
hmac_csr_rw 1.670s 34.836us 1 1 100.00
hmac_csr_aliasing 3.250s 162.306us 1 1 100.00
hmac_same_csr_outstanding 2.470s 74.106us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.610s 35.357us 1 1 100.00
hmac_tl_intg_err 3.770s 767.419us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.770s 767.419us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 11.710s 4.476ms 1 1 100.00
V3 stress_reset hmac_stress_reset 3.380s 249.480us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 39.700s 11.093ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.100s 533.790us 1 1 100.00
TOTAL 28 28 100.00