I2C Simulation Results

Tuesday April 15 2025 17:03:28 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	18.680s	6.023ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	8.340s	711.713us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.680s	77.191us	1	1	100.00
V1	csr_rw	i2c_csr_rw	2.080s	18.892us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.900s	714.471us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.210s	370.135us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.730s	27.839us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.080s	18.892us	1	1	100.00
		i2c_csr_aliasing	2.210s	370.135us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	4.440s	3.520ms	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	18.942m	600.000ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	9.910s	872.151us	1	1	100.00
V2	host_override	i2c_host_override	1.560s	60.506us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.906m	21.774ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	26.610s	1.337ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.080s	144.944us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.820s	1.136ms	1	1	100.00
		i2c_host_fifo_reset_rx	4.100s	348.433us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	50.950s	2.320ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	8.910s	6.619ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.250s	185.032us	0	1	0.00
V2	target_glitch	i2c_target_glitch	8.430s	29.809ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	7.941m	37.138ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.050s	3.711ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	25.930s	1.689ms	1	1	100.00
		i2c_target_intr_smoke	4.850s	6.031ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.900s	223.256us	1	1	100.00
		i2c_target_fifo_reset_tx	2.090s	242.308us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	9.761m	52.754ms	1	1	100.00
		i2c_target_stress_rd	25.930s	1.689ms	1	1	100.00
		i2c_target_intr_stress_wr	1.025m	13.237ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.640s	7.921ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	20.010s	4.598ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.160s	761.263us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	11.250s	10.404ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.710s	1.962ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.160s	558.665us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	9.910s	872.151us	1	1	100.00
		i2c_host_perf_precise	3.950s	220.238us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	8.910s	6.619ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.550s	105.719us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.690s	2.140ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.580s	426.121us	1	1	100.00
		i2c_target_nack_txstretch	1.920s	251.303us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.690s	431.768us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.420s	1.439ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.430s	17.830us	1	1	100.00
V2	intr_test	i2c_intr_test	1.670s	73.085us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.760s	164.314us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.760s	164.314us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.680s	77.191us	1	1	100.00
		i2c_csr_rw	2.080s	18.892us	1	1	100.00
		i2c_csr_aliasing	2.210s	370.135us	1	1	100.00
		i2c_same_csr_outstanding	1.900s	87.079us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.680s	77.191us	1	1	100.00
		i2c_csr_rw	2.080s	18.892us	1	1	100.00
		i2c_csr_aliasing	2.210s	370.135us	1	1	100.00
		i2c_same_csr_outstanding	1.900s	87.079us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.600s	173.271us	1	1	100.00
		i2c_sec_cm	1.650s	243.580us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.600s	173.271us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	31.940s	2.241ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.990s	74.741us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	8.080s	599.026us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:907) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.23303826698888196463346056141724864238239235727582303070893917637503192466548
      Line 92, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2240611331 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2240611331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.98827584086723807709105033535204368406266625230699276747793438442665933678708
      Line 96, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 599025543 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 599025543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.96974441030096870072358124793733154860992567908553830209205264479795576916374
      Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.22836311994193700896656643129041784164759721389512690132120163556405526046438
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  74740808 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 198 [0xc6])
        UVM_INFO @  74740808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.112754430052612936817766651543868705619556706026455273045334406158170811775
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10404131149 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10404131149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.91848840407259975709211522178962062823722202568358803779115709504780600370935
      Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 185032350 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
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        Name            Type                Size  Value
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