KEYMGR Simulation Results

Tuesday April 15 2025 17:03:28 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.580s	68.992us	1	1	100.00
V1	random	keymgr_random	3.510s	214.457us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.820s	67.243us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.660s	21.815us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	6.040s	260.836us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.450s	5.136ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.270s	329.411us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.660s	21.815us	1	1	100.00
		keymgr_csr_aliasing	8.450s	5.136ms	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	4.940s	379.607us	1	1	100.00
V2	sideload	keymgr_sideload	2.670s	93.863us	1	1	100.00
		keymgr_sideload_kmac	2.570s	40.103us	1	1	100.00
		keymgr_sideload_aes	5.190s	428.582us	1	1	100.00
		keymgr_sideload_otbn	6.280s	776.337us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	5.120s	483.128us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.470s	236.108us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.210s	218.895us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.520s	302.501us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	5.020s	247.912us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.130s	31.658us	1	1	100.00
V2	stress_all	keymgr_stress_all	27.920s	9.080ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.750s	39.435us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.660s	14.780us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.860s	67.495us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.860s	67.495us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.820s	67.243us	1	1	100.00
		keymgr_csr_rw	1.660s	21.815us	1	1	100.00
		keymgr_csr_aliasing	8.450s	5.136ms	1	1	100.00
		keymgr_same_csr_outstanding	3.270s	93.609us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.820s	67.243us	1	1	100.00
		keymgr_csr_rw	1.660s	21.815us	1	1	100.00
		keymgr_csr_aliasing	8.450s	5.136ms	1	1	100.00
		keymgr_same_csr_outstanding	3.270s	93.609us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	8.090s	4.617ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	8.090s	4.617ms	1	1	100.00
		keymgr_tl_intg_err	1.750s	9.898us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.870s	411.146us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.870s	411.146us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.870s	411.146us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.870s	411.146us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	8.560s	284.265us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	8.090s	4.617ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	8.090s	4.617ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.750s	9.898us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.870s	411.146us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	4.940s	379.607us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.510s	214.457us	1	1	100.00
		keymgr_csr_rw	1.660s	21.815us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.510s	214.457us	1	1	100.00
		keymgr_csr_rw	1.660s	21.815us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.510s	214.457us	1	1	100.00
		keymgr_csr_rw	1.660s	21.815us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.470s	236.108us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	5.020s	247.912us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	5.020s	247.912us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.510s	214.457us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.930s	222.263us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	8.090s	4.617ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	8.090s	4.617ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	8.090s	4.617ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	4.720s	252.252us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.470s	236.108us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	8.090s	4.617ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	8.090s	4.617ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	8.090s	4.617ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	4.720s	252.252us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	4.720s	252.252us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	8.090s	4.617ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	4.720s	252.252us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	8.090s	4.617ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	4.720s	252.252us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	7.800s	527.981us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			28	30	93.33

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:907) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.78306805467334858626194647750520284740163465896913088947638028092711890659118
      Line 595, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 527980925 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 527980925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.107351634692160732541030402785619498083369766487602492713388914382971593571812
      Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
        UVM_ERROR @   9898133 ps: (keymgr_csr_assert_fpv.sv:446) [ASSERT FAILED] attest_sw_binding_3_rd_A
        UVM_INFO @   9898133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---