| V1 |
smoke |
keymgr_dpe_smoke |
10.960s |
511.338us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
1.590s |
47.314us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
1.820s |
51.790us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
6.080s |
800.312us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
6.660s |
229.008us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
2.030s |
28.820us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
1.820s |
51.790us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
6.660s |
229.008us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
1.730s |
35.097us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
1.600s |
26.695us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
3.210s |
371.816us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
3.210s |
371.816us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
1.590s |
47.314us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.820s |
51.790us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
6.660s |
229.008us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.520s |
183.688us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
1.590s |
47.314us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.820s |
51.790us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
6.660s |
229.008us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.520s |
183.688us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
20.410s |
1.158ms |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
4.880s |
436.673us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
2.570s |
354.265us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
2.570s |
354.265us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
2.570s |
354.265us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
2.570s |
354.265us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
3.970s |
196.060us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
20.410s |
1.158ms |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
20.410s |
1.158ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |