KMAC/UNMASKED Simulation Results

Tuesday April 15 2025 17:03:28 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	15.130s	409.581us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.610s	93.141us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.750s	17.151us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.070s	291.439us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.810s	273.205us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.090s	72.000us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.750s	17.151us	1	1	100.00
		kmac_csr_aliasing	4.810s	273.205us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.640s	28.743us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.920s	22.692us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	2.413m	36.819ms	1	1	100.00
V2	burst_write	kmac_burst_write	3.544m	43.273ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	29.760m	455.389ms	1	1	100.00
		kmac_test_vectors_sha3_256	26.690s	3.380ms	1	1	100.00
		kmac_test_vectors_sha3_384	17.970s	1.467ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.800s	857.962us	1	1	100.00
		kmac_test_vectors_shake_128	34.525m	428.125ms	1	1	100.00
		kmac_test_vectors_shake_256	1.389m	5.953ms	1	1	100.00
		kmac_test_vectors_kmac	2.840s	296.577us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.130s	52.881us	1	1	100.00
V2	sideload	kmac_sideload	3.426m	15.937ms	1	1	100.00
V2	app	kmac_app	3.778m	14.719ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.363m	46.242ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.321m	28.977ms	1	1	100.00
V2	error	kmac_error	4.150m	18.001ms	1	1	100.00
V2	key_error	kmac_key_error	3.350s	555.066us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.320s	145.773us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	19.470s	1.201ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	14.520s	3.466ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	19.210s	2.998ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.910s	106.446us	1	1	100.00
V2	stress_all	kmac_stress_all	8.928m	219.086ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.620s	15.507us	1	1	100.00
V2	alert_test	kmac_alert_test	1.630s	18.811us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.200s	110.599us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.200s	110.599us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.610s	93.141us	1	1	100.00
		kmac_csr_rw	1.750s	17.151us	1	1	100.00
		kmac_csr_aliasing	4.810s	273.205us	1	1	100.00
		kmac_same_csr_outstanding	2.080s	25.274us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.610s	93.141us	1	1	100.00
		kmac_csr_rw	1.750s	17.151us	1	1	100.00
		kmac_csr_aliasing	4.810s	273.205us	1	1	100.00
		kmac_same_csr_outstanding	2.080s	25.274us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.770s	63.474us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.770s	63.474us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.770s	63.474us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.770s	63.474us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.050s	16.487us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	21.780s	5.795ms	1	1	100.00
		kmac_tl_intg_err	3.840s	564.213us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.840s	564.213us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.910s	106.446us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	15.130s	409.581us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.426m	15.937ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.770s	63.474us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	21.780s	5.795ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	21.780s	5.795ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	21.780s	5.795ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	15.130s	409.581us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.910s	106.446us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	21.780s	5.795ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.306m	15.849ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	15.130s	409.581us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	20.400s	4.264ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.52447527744409878137667547842881563524948815843219928028427518082625397141089
      Line 98, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4264210176 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 4264210176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.109432871197863098723709683382511162074559675871367755923067992712367046470593
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
        UVM_ERROR @  16487456 ps: (kmac_csr_assert_fpv.sv:517) [ASSERT FAILED] prefix_5_rd_A
        UVM_INFO @  16487456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---