ROM_CTRL/32KB Simulation Results

Tuesday April 15 2025 17:03:28 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.090s	606.159us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	11.030s	591.679us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	3.990s	385.558us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	3.900s	372.223us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.440s	165.127us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.510s	393.673us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	3.990s	385.558us	1	1	100.00
		rom_ctrl_csr_aliasing	5.440s	165.127us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.980s	281.108us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.970s	169.618us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.650s	316.440us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	16.180s	592.914us	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	10.870s	306.243us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	5.360s	169.010us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	7.990s	695.484us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	7.990s	695.484us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	11.030s	591.679us	1	1	100.00
		rom_ctrl_csr_rw	3.990s	385.558us	1	1	100.00
		rom_ctrl_csr_aliasing	5.440s	165.127us	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.450s	233.254us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	11.030s	591.679us	1	1	100.00
		rom_ctrl_csr_rw	3.990s	385.558us	1	1	100.00
		rom_ctrl_csr_aliasing	5.440s	165.127us	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.450s	233.254us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	24.300s	2.469ms	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	20.430s	11.204ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.213m	1.594ms	1	1	100.00
		rom_ctrl_tl_intg_err	24.150s	724.238us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.213m	1.594ms	1	1	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.213m	1.594ms	1	1	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	24.300s	2.469ms	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	24.300s	2.469ms	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	24.300s	2.469ms	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	24.300s	2.469ms	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	24.300s	2.469ms	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.213m	1.594ms	1	1	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.213m	1.594ms	1	1	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.090s	606.159us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.090s	606.159us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.090s	606.159us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	24.150s	724.238us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	24.300s	2.469ms	0	1	0.00
		rom_ctrl_kmac_err_chk	10.870s	306.243us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	24.300s	2.469ms	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	24.300s	2.469ms	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	24.300s	2.469ms	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	20.430s	11.204ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.213m	1.594ms	1	1	100.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	4.302m	8.396ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:324) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.109028099085895879059245940103836757703820823564730925689088060270796829584103
      Line 86, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 2469006015 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:324) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 2469006015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---