ROM_CTRL/64KB Simulation Results

Tuesday April 15 2025 17:03:28 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.660s 775.474us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.420s 542.527us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.790s 1.691ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.470s 2.098ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.870s 218.666us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 8.400s 312.317us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.790s 1.691ms 1 1 100.00
rom_ctrl_csr_aliasing 6.870s 218.666us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.030s 535.374us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 9.210s 534.503us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.160s 1.054ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 22.540s 911.969us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 12.300s 1.426ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.360s 210.891us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 10.000s 218.982us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 10.000s 218.982us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.420s 542.527us 1 1 100.00
rom_ctrl_csr_rw 6.790s 1.691ms 1 1 100.00
rom_ctrl_csr_aliasing 6.870s 218.666us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.480s 214.055us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.420s 542.527us 1 1 100.00
rom_ctrl_csr_rw 6.790s 1.691ms 1 1 100.00
rom_ctrl_csr_aliasing 6.870s 218.666us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.480s 214.055us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.095m 6.032ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 33.670s 1.122ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.015m 3.107ms 1 1 100.00
rom_ctrl_tl_intg_err 1.077m 686.591us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.015m 3.107ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.015m 3.107ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.095m 6.032ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.095m 6.032ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.095m 6.032ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.095m 6.032ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.095m 6.032ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.015m 3.107ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.015m 3.107ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.660s 775.474us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.660s 775.474us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.660s 775.474us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.077m 686.591us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.095m 6.032ms 1 1 100.00
rom_ctrl_kmac_err_chk 12.300s 1.426ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.095m 6.032ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.095m 6.032ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.095m 6.032ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 33.670s 1.122ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.015m 3.107ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.440m 6.385ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00