SPI_DEVICE/1R1W Simulation Results

Tuesday April 15 2025 17:03:28 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.090m	64.125ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.850s	44.357us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.970s	136.769us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	18.300s	6.277ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.440s	1.118ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.220s	42.189us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.970s	136.769us	1	1	100.00
		spi_device_csr_aliasing	16.440s	1.118ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.530s	22.494us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.950s	135.974us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.720s	14.402us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.620s	2.003us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.590s	1.306us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.410s	607.317us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.410s	607.317us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.240s	5.701ms	1	1	100.00
		spi_device_tpm_sts_read	1.830s	142.323us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	15.890s	6.932ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.160s	418.786us	1	1	100.00
		spi_device_flash_all	55.800s	34.803ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	10.150s	13.142ms	1	1	100.00
		spi_device_flash_all	55.800s	34.803ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	10.150s	13.142ms	1	1	100.00
		spi_device_flash_all	55.800s	34.803ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	55.800s	34.803ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.160s	69.380us	1	1	100.00
		spi_device_flash_all	55.800s	34.803ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.160s	69.380us	1	1	100.00
		spi_device_flash_all	55.800s	34.803ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.160s	69.380us	1	1	100.00
		spi_device_flash_all	55.800s	34.803ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.160s	69.380us	1	1	100.00
		spi_device_flash_all	55.800s	34.803ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.160s	69.380us	1	1	100.00
		spi_device_flash_all	55.800s	34.803ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.790s	469.380us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	1.177m	175.884ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.177m	175.884ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.177m	175.884ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.020s	87.818us	1	1	100.00
		spi_device_read_buffer_direct	3.400s	284.744us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.177m	175.884ms	1	1	100.00
		spi_device_flash_all	55.800s	34.803ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	55.800s	34.803ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	55.800s	34.803ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.040s	275.273us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.040s	275.273us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.090m	64.125ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.552m	79.368ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.231m	13.926ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.720s	49.464us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.710s	61.264us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.360s	128.766us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.360s	128.766us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.850s	44.357us	1	1	100.00
		spi_device_csr_rw	1.970s	136.769us	1	1	100.00
		spi_device_csr_aliasing	16.440s	1.118ms	1	1	100.00
		spi_device_same_csr_outstanding	3.140s	483.136us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.850s	44.357us	1	1	100.00
		spi_device_csr_rw	1.970s	136.769us	1	1	100.00
		spi_device_csr_aliasing	16.440s	1.118ms	1	1	100.00
		spi_device_same_csr_outstanding	3.140s	483.136us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.880s	261.396us	1	1	100.00
		spi_device_tl_intg_err	17.240s	872.519us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	17.240s	872.519us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.305m	17.444ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.12793332427976768807157313993258510471219740949996479298405148006026518258440
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1075897 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[72])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1075897 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1075897 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[968])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.35602964130856902031341921357566684920619774931504695613936569306750257128426
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    713828 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    713828 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @    749828 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1ad34d [110101101001101001101] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @    749828 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x1ad34d [110101101001101001101] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])