SPI_HOST Simulation Results

Tuesday April 15 2025 17:03:28 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	34.000s	1.987ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	22.584us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	26.182us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	100.603us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	74.251us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	168.988us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	26.182us	1	1	100.00
		spi_host_csr_aliasing	4.000s	74.251us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	18.198us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	33.306us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	13.000s	110.651us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	182.810us	1	1	100.00
		spi_host_error_cmd	4.000s	18.689us	1	1	100.00
		spi_host_event	11.000s	3.072ms	1	1	100.00
V2	clock_rate	spi_host_speed	15.000s	168.902us	1	1	100.00
V2	speed	spi_host_speed	15.000s	168.902us	1	1	100.00
V2	chip_select_timing	spi_host_speed	15.000s	168.902us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	22.000s	774.811us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	1.125ms	1	1	100.00
V2	cpol_cpha	spi_host_speed	15.000s	168.902us	1	1	100.00
V2	full_cycle	spi_host_speed	15.000s	168.902us	1	1	100.00
V2	duplex	spi_host_smoke	34.000s	1.987ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	34.000s	1.987ms	1	1	100.00
V2	stress_all	spi_host_stress_all	38.000s	5.038ms	1	1	100.00
V2	spien	spi_host_spien	9.000s	261.408us	1	1	100.00
V2	stall	spi_host_status_stall	29.000s	4.131ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	7.000s	872.055us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	182.810us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	80.901us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	33.440us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	147.182us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	147.182us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	22.584us	1	1	100.00
		spi_host_csr_rw	4.000s	26.182us	1	1	100.00
		spi_host_csr_aliasing	4.000s	74.251us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	53.808us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	22.584us	1	1	100.00
		spi_host_csr_rw	4.000s	26.182us	1	1	100.00
		spi_host_csr_aliasing	4.000s	74.251us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	53.808us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	148.123us	1	1	100.00
		spi_host_sec_cm	4.000s	69.994us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	148.123us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	36.550m	69.645ms	1	1	100.00
		TOTAL			26	26	100.00