SRAM_CTRL/MAIN Simulation Results

Tuesday April 15 2025 17:03:28 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	58.480s	992.008us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.550s	16.722us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.620s	15.833us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.350s	42.357us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.680s	46.798us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.170s	361.397us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.620s	15.833us	1	1	100.00
		sram_ctrl_csr_aliasing	1.680s	46.798us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.041m	16.417ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.771m	4.989ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	14.223m	25.144ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.084m	3.472ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	21.871m	26.416ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	8.166m	11.310ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	24.690s	5.396ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.762m	13.813ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	20.510s	1.721ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.414m	8.995ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	21.110s	2.962ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	47.950s	6.515ms	1	1	100.00
		sram_ctrl_throughput_w_readback	13.870s	3.242ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.643m	175.914ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.260s	2.099ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.110h	80.769ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.600s	28.081us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.340s	135.058us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.340s	135.058us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.550s	16.722us	1	1	100.00
		sram_ctrl_csr_rw	1.620s	15.833us	1	1	100.00
		sram_ctrl_csr_aliasing	1.680s	46.798us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	48.341us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.550s	16.722us	1	1	100.00
		sram_ctrl_csr_rw	1.620s	15.833us	1	1	100.00
		sram_ctrl_csr_aliasing	1.680s	46.798us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	48.341us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	29.830s	7.369ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.620s	1.897us	0	1	0.00
		sram_ctrl_tl_intg_err	2.130s	145.334us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.620s	1.897us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.130s	145.334us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.643m	175.914ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.643m	175.914ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.620s	15.833us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.762m	13.813ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.762m	13.813ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.762m	13.813ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	24.690s	5.396ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.020s	2.105ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	29.830s	7.369ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	6.020s	2.740ms	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	58.480s	992.008us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	58.480s	992.008us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.762m	13.813ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.620s	1.897us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	24.690s	5.396ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.620s	1.897us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.620s	1.897us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	58.480s	992.008us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.620s	1.897us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	11.110s	1.041ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.12409690864002752954590930223330119234952867236801503516103690235444218074538
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2740165020 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x12) != exp (0x4a)
        UVM_INFO @ 2740165020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.105203688802216554183581812326215031040126150443881895960362390976397515942171
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   1896850 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   1896850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---