SRAM_CTRL/RET Simulation Results

Tuesday April 15 2025 17:03:28 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	41.240s	2.651ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.470s	28.646us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.430s	52.895us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.760s	31.646us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.440s	49.629us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.510s	46.736us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.430s	52.895us	1	1	100.00
		sram_ctrl_csr_aliasing	1.440s	49.629us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.470s	142.257us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.450s	236.467us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.865m	27.813ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.225m	2.785ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	23.820s	5.824ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1.015m	1.975ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.720s	637.121us	1	1	100.00
V2	executable	sram_ctrl_executable	9.385m	68.741ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	13.810s	621.513us	1	1	100.00
		sram_ctrl_partial_access_b2b	6.530m	85.474ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	34.180s	121.977us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	12.510s	581.623us	1	1	100.00
		sram_ctrl_throughput_w_readback	54.050s	2.532ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.607m	13.176ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.000s	85.073us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	32.943m	68.663ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.590s	32.926us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.870s	87.311us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.870s	87.311us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.470s	28.646us	1	1	100.00
		sram_ctrl_csr_rw	1.430s	52.895us	1	1	100.00
		sram_ctrl_csr_aliasing	1.440s	49.629us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.560s	107.458us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.470s	28.646us	1	1	100.00
		sram_ctrl_csr_rw	1.430s	52.895us	1	1	100.00
		sram_ctrl_csr_aliasing	1.440s	49.629us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.560s	107.458us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.430s	266.708us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.950s	7.362us	0	1	0.00
		sram_ctrl_tl_intg_err	2.830s	365.322us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.950s	7.362us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.830s	365.322us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.607m	13.176ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.607m	13.176ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.430s	52.895us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	9.385m	68.741ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	9.385m	68.741ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	9.385m	68.741ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.720s	637.121us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.640s	112.093us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.430s	266.708us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.970s	140.074us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	41.240s	2.651ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	41.240s	2.651ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	9.385m	68.741ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.950s	7.362us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.720s	637.121us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.950s	7.362us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.950s	7.362us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	41.240s	2.651ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.950s	7.362us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.998m	2.122ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.61013908598433136316486470730956709695858840534458888177553064719367467925143
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7362321 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7362321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---