UART Simulation Results

Tuesday April 15 2025 17:03:28 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.550s	694.761us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.380s	26.680us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.530s	24.215us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.250s	129.888us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.500s	62.830us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.110s	76.217us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.530s	24.215us	1	1	100.00
		uart_csr_aliasing	1.500s	62.830us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	25.380s	107.744ms	1	1	100.00
V2	parity	uart_smoke	2.550s	694.761us	1	1	100.00
		uart_tx_rx	25.380s	107.744ms	1	1	100.00
V2	parity_error	uart_intr	10.840s	42.308ms	1	1	100.00
		uart_rx_parity_err	24.900s	89.533ms	1	1	100.00
V2	watermark	uart_tx_rx	25.380s	107.744ms	1	1	100.00
		uart_intr	10.840s	42.308ms	1	1	100.00
V2	fifo_full	uart_fifo_full	18.550s	33.348ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	26.550s	21.918ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	12.130s	20.381ms	1	1	100.00
V2	rx_frame_err	uart_intr	10.840s	42.308ms	1	1	100.00
V2	rx_break_err	uart_intr	10.840s	42.308ms	1	1	100.00
V2	rx_timeout	uart_intr	10.840s	42.308ms	1	1	100.00
V2	perf	uart_perf	55.710s	1.664ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.750s	5.868ms	1	1	100.00
V2	line_loopback	uart_loopback	3.750s	5.868ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	27.890s	37.818ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.040s	2.603ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.030s	1.744ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	9.340s	4.707ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.238m	103.391ms	1	1	100.00
V2	stress_all	uart_stress_all	14.814m	312.334ms	1	1	100.00
V2	alert_test	uart_alert_test	1.740s	22.975us	1	1	100.00
V2	intr_test	uart_intr_test	1.410s	87.754us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.070s	97.633us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.070s	97.633us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.380s	26.680us	1	1	100.00
		uart_csr_rw	1.530s	24.215us	1	1	100.00
		uart_csr_aliasing	1.500s	62.830us	1	1	100.00
		uart_same_csr_outstanding	1.640s	21.193us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.380s	26.680us	1	1	100.00
		uart_csr_rw	1.530s	24.215us	1	1	100.00
		uart_csr_aliasing	1.500s	62.830us	1	1	100.00
		uart_same_csr_outstanding	1.640s	21.193us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.700s	63.722us	1	1	100.00
		uart_tl_intg_err	1.810s	42.967us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.810s	42.967us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	41.880s	42.126ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00