CHIP Simulation Results

Tuesday April 15 2025 17:03:28 UTC

GitHub Revision: `3527f96`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.507m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.507m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.035m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	59.205s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	11.240s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.156m	5.560ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.156m	5.560ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.156m	5.560ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	1.484m		0	1	0.00
		chip_sw_example_manufacturer	2.481m		0	1	0.00
		chip_sw_example_concurrency	4.302m	3.588ms	1	1	100.00
		chip_sw_uart_smoketest_signed	12.742s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.570s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	11.430s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	11.430s		0	1	0.00
V1	xbar_smoke	xbar_smoke	17.880s	57.613us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.241m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.332m	10.086ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.479m	5.541ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	15.627s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	26.171s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	19.469s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	12.963s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.450s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.450s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.965m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	21.122s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.332m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.332m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	4.034m	4.882ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.530m	3.723ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.174m	5.675ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.496s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.265s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	10.615m	17.883ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.610m	6.875ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	20.366m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	20.366m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.384s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.359s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.359s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.703s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.808m	3.637ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.448m	4.791ms	1	1	100.00
		chip_sw_aes_idle	4.691m	4.502ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.023m	3.434ms	1	1	100.00
		chip_sw_kmac_idle	3.768m	5.167ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	14.057s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.163s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	12.919s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	10.379s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.020s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.706s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.597s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.966s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.674s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.624s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.306s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.020s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.706s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.597s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.966s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.674s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.624s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.306s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.408s		0	1	0.00
		chip_sw_aes_enc_jitter_en	47.980s	10.240us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.520s	10.300us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	53.490s	10.160us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	46.550s	10.300us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.006s		0	1	0.00
		chip_sw_clkmgr_jitter	4.026m	4.118ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.194m	3.638ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.652s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	48.290s	10.340us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	47.550s	10.120us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1.299m	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	1.001m	10.400us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	1.006m	10.320us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.732s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	12.036s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.962s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	13.301s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	19.791m	12.731ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.631m	13.572ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	10.359s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.355s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.631m	13.572ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	14.867s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	13.091s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	11.721s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	15.504s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.915s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	19.791m	12.731ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.174m	5.675ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	23.903m	20.018ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.818m	12.022ms	0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	11.530m	30.017ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.734m	4.921ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	19.791m	12.731ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	14.059s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	14.372s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	19.791m	12.731ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	14.178s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	11.530m	30.017ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.844s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.470s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.927s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.595s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.708s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.699s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	14.372s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	13.407s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	14.356s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	13.407s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	13.407s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	13.407s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	8.315m	20.010ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.336s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	17.905s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	10.978s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	18.757s		0	1	0.00
		chip_sw_lc_ctrl_transition	13.407s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.303m	20.010ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	7.948m	14.283ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.009s		0	1	0.00
		chip_prim_tl_access	14.498m	20.869ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.020s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.706s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.597s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.966s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.674s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.624s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.306s		0	1	0.00
		chip_rv_dm_lc_disabled	10.615m	17.883ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.124m	4.338ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	47.980s	10.240us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.747m	3.636ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.691m	4.502ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.249m	3.803ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	46.520s	10.300us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.023m	3.434ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.804m	3.616ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.810m	3.709ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	46.550s	10.300us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.303m	20.010ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	13.407s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	39.560s	10.200us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.220m	5.742ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.768m	5.167ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.402s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.402s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.746s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.133m	4.853ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	11.496s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.303m	20.010ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	53.490s	10.160us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	11.308s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	12.408s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.448m	4.791ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.448m	4.791ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.448m	4.791ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.749m	6.855ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	7.948m	14.283ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	7.948m	14.283ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.307m	6.514ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.006s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.009s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	19.791m	12.731ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.332m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	13.407s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.749m	6.855ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.303m	20.010ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	11.307m	6.514ms	0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	3.661m	3.759ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.749m	6.855ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.303m	20.010ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	11.307m	6.514ms	0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	3.661m	3.759ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	13.407s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.049s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	14.356s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.336s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	17.905s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	10.978s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	18.757s		0	1	0.00
		chip_sw_lc_ctrl_transition	13.407s		0	1	0.00
		chip_prim_tl_access	14.498m	20.869ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	14.498m	20.869ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	11.366s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	20.476s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	12.036s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.408s		0	1	0.00
		chip_sw_aes_enc_jitter_en	47.980s	10.240us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.520s	10.300us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	53.490s	10.160us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	46.550s	10.300us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.006s		0	1	0.00
		chip_sw_clkmgr_jitter	4.026m	4.118ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.820m	7.644ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.820m	7.644ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.705m	3.935ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.661m	5.777ms	1	1	100.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.302m	5.173ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.264m	4.883ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.323m	3.881ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.276m	3.282ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.661m	3.759ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	23.903m	20.018ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	23.903m	20.018ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.930m	5.150ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.038m	3.439ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.791m	3.169ms	1	1	100.00
		chip_sw_csrng_smoketest	3.216m	5.337ms	1	1	100.00
		chip_sw_gpio_smoketest	4.079m	4.486ms	1	1	100.00
		chip_sw_hmac_smoketest	3.766m	3.849ms	1	1	100.00
		chip_sw_kmac_smoketest	3.829m	4.397ms	1	1	100.00
		chip_sw_otbn_smoketest	4.960m	5.920ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.817m	4.652ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.813m	4.162ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.729m	5.071ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.611m	5.779ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.999m	4.887ms	1	1	100.00
		chip_sw_uart_smoketest	3.714m	4.377ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.923s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	12.742s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.241m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	11.334s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.791m	5.849ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.486m	6.786ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.548m	4.589ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.359m	5.500ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	12.839s		0	1	0.00
		chip_rv_dm_lc_disabled	10.615m	17.883ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	11.734s		0	1	0.00
		chip_sw_lc_walkthrough_prod	12.010s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	12.497s		0	1	0.00
		chip_sw_lc_walkthrough_rma	13.200s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	12.839s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	12.719s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.442s		0	1	0.00
		rom_volatile_raw_unlock	10.769s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	14.652s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.100m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.121m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.483m	5.507ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.483m	5.507ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	11.430s		0	1	0.00
		chip_same_csr_outstanding	10.040s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	11.430s		0	1	0.00
		chip_same_csr_outstanding	10.040s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	40.580s	37.286us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	10.280s	11.702us	1	1	100.00
		xbar_smoke_large_delays	4.997m	2.559ms	1	1	100.00
		xbar_smoke_slow_rsp	5.823m	2.129ms	1	1	100.00
		xbar_random_zero_delays	8.210s	9.989us	1	1	100.00
		xbar_random_large_delays	17.230m	8.781ms	1	1	100.00
		xbar_random_slow_rsp	27.403m	10.463ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.075m	43.151us	1	1	100.00
		xbar_error_and_unmapped_addr	34.910s	75.890us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	47.560s	53.422us	1	1	100.00
		xbar_error_and_unmapped_addr	34.910s	75.890us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.649m	429.382us	1	1	100.00
		xbar_access_same_device_slow_rsp	41.397m	16.406ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	33.380s	31.625us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	4.817m	207.973us	1	1	100.00
		xbar_stress_all_with_error	1.967m	335.887us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	12.815m	641.929us	1	1	100.00
		xbar_stress_all_with_reset_error	21.606m	2.955ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	11.036s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.691s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.064s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	10.512s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.409s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.273s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.112s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.112s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.047s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.257s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.153s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.952s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.281s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.523s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.637s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	10.936s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.537s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.894s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.751s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.760s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.028s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.785s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.683s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.411s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	11.790s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	11.760s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	11.621s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	11.631s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	11.909s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.684s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.860s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.487s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.418s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.285s		0	1	0.00
		rom_e2e_asm_init_dev	10.935s		0	1	0.00
		rom_e2e_asm_init_prod	11.391s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.996s		0	1	0.00
		rom_e2e_asm_init_rma	11.289s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.556s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.289s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.935s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	13.040s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.330m	4.496ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.928m	4.647ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	10.653s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.766s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.536s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.555s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	19.791m	12.731ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	12.169s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.307m	15.906ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	10.777s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	10.077s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	10.653s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.766s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.536s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.434s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.949s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.399s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.293m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.734m	13.606ms	1	1	100.00
		chip_plic_all_irqs_0	9.713m	6.516ms	1	1	100.00
		chip_plic_all_irqs_10	9.794m	6.232ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.717m	3.723ms	1	1	100.00
		chip_sw_dma_abort	3.782m	4.635ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.521s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.884s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.492s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	12.916s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.354s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.954s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.277s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.411s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.626s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.875s		0	1	0.00
		chip_sw_mbx_smoketest	4.325m	5.049ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 143 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.98751992879775957734593783505871530746044251287819734531023145160469087122002
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Target //sw/device/tests:example_test_from_rom_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (e39fd6)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (2d2e87)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 74.199s, Critical Path: 0.05s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.68897234774155084910312646633473741873754605632699444520993249786436437210413
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (8a8261)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 137.752s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.54786597107701812141691232600361058708492807705458569421904042469174225889005
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (92aa0b)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 129.680s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.47729154559979583753864218088247490212010245898765892183754298998777392720341
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (68f607)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 107.053s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.10422477757237090213132103398164990567890693123068050420557025100804742361949
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (20615e)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 10.961s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 138 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.26087708122492144681141333673319355978877087077615973542382329323690010498874
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.46845165986059493141758617427515916024535274703035261481915826337316324802506
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.27514459670364970726796955105889002505012887505508360411183482624540747706056
    Line 406, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.105165121842105757252997784056343642209600975906958904149535158619487515020605
    Line 409, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.46209693630200668146031931612564711493733185129421705363658610250005850554300
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_rstmgr_sw_req has 1 failures.

0.chip_sw_rstmgr_sw_req.56530847327131465511386870901847431635702585205991746237369684583051600936161
Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest/run.log

  UVM_ERROR @ 12021.932197 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12021.932197 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_alert_info has 1 failures.

0.chip_sw_rstmgr_alert_info.91324204973812367821929902940839345412824577267464302924483470457776141310499
Line 445, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30017.241338 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30017.241338 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.15442238140383019503638794176941425073312061962355328694756178399446966597147
Line 464, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20017.904026 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20017.904026 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.77962682697226973482574122984775977078437114178023897030259516139166716762916
Line 436, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18016.951053 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.951053 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.12257996940317226911143081856335783810037671120207236884027943990343024088096
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.43676060323966470808501302007869923809319077514736221356930372157230729945672
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.56368995785785860259790606380118758447787075954071940717501533269877621828742
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage * key has 2 failures:
- Test chip_sw_keymgr_dpe_key_derivation has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation.43287892745738621788701433718934681446188241881764634567842907768379658037880
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log
```
  UVM_FATAL @ 20010.380001 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage 0 key
  UVM_INFO @ 20010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_prod.60343419834484896971045725055506627073564117611841540884289636070138030958997
    Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
```
  UVM_FATAL @ 20010.380001 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage 0 key
  UVM_INFO @ 20010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.98841434195109323703997418801342834009188159389054384590188630151179512460998
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4881.962025 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h31066e0b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h1  a_user: 'h24897  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4881.962025 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.86637013447366419601487881329203326856285498134652657940239023755819256598391
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3723.289128 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h1cf356c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h1  a_user: 'h248d6  d_param: 'h0  d_source: 'h38  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3723.289128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.77304192197169976440233997579122011464206047058213950910259671719933692244225
    Line 464, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5541.189950 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5541.189950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.40085899135119194785763304374490108949705280497206587069977229150550815846632
    Line 437, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3934.703932 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3934.703932 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.55725810385407723144798384280552518008846811398833996666075407124377756589263
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4882.892870 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4882.892870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.65300855684468240185147655395973990625323505952615890848189173047921661510135
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_sram_ctrl_scrambled_access has 1 failures.
  - 0.chip_sw_sram_ctrl_scrambled_access.102636203570209960202582392462934842951466873498772054325280433883490382456616
    Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access/latest/run.log
```
  UVM_ERROR @ 6514.411094 us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 6514.411094 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.41626588365200554526179637113521651671379633534592803097521589751147512238432
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 5506.981024 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 5506.981024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.47629103339272385161896290457698082668636342571611752022770668432510925821823
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.91257508892939657993878675299534180146331645552602935137290511754561738550834
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4635.350620 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4635.350620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```