DMA Simulation Results

Wednesday April 16 2025 17:02:56 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	1.266ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	7.000s	1.923ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	740.171us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	21.560us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	51.307us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.000s	591.280us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	9.000s	974.244us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	369.462us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	51.307us	1	1	100.00
		dma_csr_aliasing	9.000s	974.244us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	53.000s	15.824ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	3.333m	16.543ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	20.333m	115.454ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	20.683m	128.113ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	3.333m	16.543ms	1	1	100.00
V2	dma_abort	dma_abort	10.000s	1.689ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.733m	33.623ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	13.478us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	39.895us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	39.895us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	21.560us	1	1	100.00
		dma_csr_rw	4.000s	51.307us	1	1	100.00
		dma_csr_aliasing	9.000s	974.244us	1	1	100.00
		dma_same_csr_outstanding	5.000s	86.031us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	21.560us	1	1	100.00
		dma_csr_rw	4.000s	51.307us	1	1	100.00
		dma_csr_aliasing	9.000s	974.244us	1	1	100.00
		dma_same_csr_outstanding	5.000s	86.031us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	26.000s	259.443us	1	1	100.00
		dma_generic_stress	20.683m	128.113ms	1	1	100.00
		dma_handshake_stress	3.333m	16.543ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	6.000s	180.015us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.983m	40.850ms	1	1	100.00
		dma_longer_transfer	8.000s	257.737us	1	1	100.00
		TOTAL			21	21	100.00