EDN Simulation Results

Wednesday April 16 2025 17:02:56 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.920s 18.621us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.540s 16.602us 1 1 100.00
V1 csr_rw edn_csr_rw 1.570s 36.145us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.270s 180.566us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.760s 31.011us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.070s 23.633us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.570s 36.145us 1 1 100.00
edn_csr_aliasing 1.760s 31.011us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.340s 37.483us 1 1 100.00
V2 csrng_commands edn_genbits 2.340s 37.483us 1 1 100.00
V2 genbits edn_genbits 2.340s 37.483us 1 1 100.00
V2 interrupts edn_intr 1.970s 25.183us 1 1 100.00
V2 alerts edn_alert 2.170s 100.038us 1 1 100.00
V2 errs edn_err 1.940s 18.903us 1 1 100.00
V2 disable edn_disable 1.750s 35.518us 1 1 100.00
edn_disable_auto_req_mode 1.880s 105.776us 1 1 100.00
V2 stress_all edn_stress_all 3.370s 129.824us 1 1 100.00
V2 intr_test edn_intr_test 1.620s 15.815us 1 1 100.00
V2 alert_test edn_alert_test 1.810s 41.644us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.530s 131.453us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.530s 131.453us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.540s 16.602us 1 1 100.00
edn_csr_rw 1.570s 36.145us 1 1 100.00
edn_csr_aliasing 1.760s 31.011us 1 1 100.00
edn_same_csr_outstanding 1.700s 80.013us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.540s 16.602us 1 1 100.00
edn_csr_rw 1.570s 36.145us 1 1 100.00
edn_csr_aliasing 1.760s 31.011us 1 1 100.00
edn_same_csr_outstanding 1.700s 80.013us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 7.700s 1.388ms 1 1 100.00
edn_tl_intg_err 2.960s 96.760us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 2.240s 22.006us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 2.170s 100.038us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.700s 1.388ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.700s 1.388ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.700s 1.388ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.700s 1.388ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.170s 100.038us 1 1 100.00
edn_sec_cm 7.700s 1.388ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.170s 100.038us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.960s 96.760us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets