HMAC Simulation Results

Wednesday April 16 2025 17:02:56 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 5.510s 119.473us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.740s 39.767us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.730s 42.215us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.390s 945.714us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.030s 131.589us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.970s 17.548us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.730s 42.215us 1 1 100.00
hmac_csr_aliasing 5.030s 131.589us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 13.140s 608.362us 1 1 100.00
V2 back_pressure hmac_back_pressure 56.830s 1.323ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.970s 187.579us 1 1 100.00
hmac_test_sha384_vectors 6.442m 43.963ms 1 1 100.00
hmac_test_sha512_vectors 20.410s 878.591us 1 1 100.00
hmac_test_hmac256_vectors 9.110s 921.086us 1 1 100.00
hmac_test_hmac384_vectors 12.090s 389.322us 1 1 100.00
hmac_test_hmac512_vectors 11.470s 267.660us 1 1 100.00
V2 burst_wr hmac_burst_wr 13.770s 333.856us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 7.129m 13.642ms 1 1 100.00
V2 error hmac_error 53.510s 2.857ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.564m 29.303ms 1 1 100.00
V2 save_and_restore hmac_smoke 5.510s 119.473us 1 1 100.00
hmac_long_msg 13.140s 608.362us 1 1 100.00
hmac_back_pressure 56.830s 1.323ms 1 1 100.00
hmac_datapath_stress 7.129m 13.642ms 1 1 100.00
hmac_burst_wr 13.770s 333.856us 1 1 100.00
hmac_stress_all 1.850s 27.128us 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 5.510s 119.473us 1 1 100.00
hmac_long_msg 13.140s 608.362us 1 1 100.00
hmac_back_pressure 56.830s 1.323ms 1 1 100.00
hmac_datapath_stress 7.129m 13.642ms 1 1 100.00
hmac_wipe_secret 1.564m 29.303ms 1 1 100.00
hmac_test_sha256_vectors 8.970s 187.579us 1 1 100.00
hmac_test_sha384_vectors 6.442m 43.963ms 1 1 100.00
hmac_test_sha512_vectors 20.410s 878.591us 1 1 100.00
hmac_test_hmac256_vectors 9.110s 921.086us 1 1 100.00
hmac_test_hmac384_vectors 12.090s 389.322us 1 1 100.00
hmac_test_hmac512_vectors 11.470s 267.660us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 5.510s 119.473us 1 1 100.00
hmac_long_msg 13.140s 608.362us 1 1 100.00
hmac_back_pressure 56.830s 1.323ms 1 1 100.00
hmac_datapath_stress 7.129m 13.642ms 1 1 100.00
hmac_burst_wr 13.770s 333.856us 1 1 100.00
hmac_error 53.510s 2.857ms 1 1 100.00
hmac_wipe_secret 1.564m 29.303ms 1 1 100.00
hmac_test_sha256_vectors 8.970s 187.579us 1 1 100.00
hmac_test_sha384_vectors 6.442m 43.963ms 1 1 100.00
hmac_test_sha512_vectors 20.410s 878.591us 1 1 100.00
hmac_test_hmac256_vectors 9.110s 921.086us 1 1 100.00
hmac_test_hmac384_vectors 12.090s 389.322us 1 1 100.00
hmac_test_hmac512_vectors 11.470s 267.660us 1 1 100.00
hmac_stress_all 1.850s 27.128us 1 1 100.00
V2 stress_all hmac_stress_all 1.850s 27.128us 1 1 100.00
V2 alert_test hmac_alert_test 1.400s 14.780us 1 1 100.00
V2 intr_test hmac_intr_test 1.530s 49.162us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.890s 602.798us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.890s 602.798us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.740s 39.767us 1 1 100.00
hmac_csr_rw 1.730s 42.215us 1 1 100.00
hmac_csr_aliasing 5.030s 131.589us 1 1 100.00
hmac_same_csr_outstanding 2.320s 1.412ms 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.740s 39.767us 1 1 100.00
hmac_csr_rw 1.730s 42.215us 1 1 100.00
hmac_csr_aliasing 5.030s 131.589us 1 1 100.00
hmac_same_csr_outstanding 2.320s 1.412ms 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.850s 83.889us 1 1 100.00
hmac_tl_intg_err 3.430s 2.917ms 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.430s 2.917ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 5.510s 119.473us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.150s 182.405us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 3.475m 13.477ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.360s 141.994us 1 1 100.00
TOTAL 28 28 100.00