I2C Simulation Results

Wednesday April 16 2025 17:02:56 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	25.900s	1.889ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	21.350s	1.820ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.580s	23.591us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.810s	20.467us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.060s	117.252us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	3.010s	432.498us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.910s	71.257us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.810s	20.467us	1	1	100.00
		i2c_csr_aliasing	3.010s	432.498us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	4.910s	611.036us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	13.428m	21.933ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	11.713m	23.358ms	1	1	100.00
V2	host_override	i2c_host_override	1.720s	17.734us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.632m	20.902ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	33.010s	1.511ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.900s	434.006us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.920s	402.219us	1	1	100.00
		i2c_host_fifo_reset_rx	5.690s	198.289us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.299m	3.379ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	5.910s	769.719us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.770s	46.154us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.930s	13.351ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	40.640s	39.032ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.950s	4.695ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	40.530s	4.609ms	1	1	100.00
		i2c_target_intr_smoke	3.440s	1.267ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.930s	151.207us	1	1	100.00
		i2c_target_fifo_reset_tx	1.810s	166.890us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	10.350s	13.119ms	1	1	100.00
		i2c_target_stress_rd	40.530s	4.609ms	1	1	100.00
		i2c_target_intr_stress_wr	43.570s	22.005ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.910s	1.455ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	7.900s	3.745ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.350s	1.167ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	21.250s	10.034ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.410s	436.364us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.120s	138.640us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	11.713m	23.358ms	1	1	100.00
		i2c_host_perf_precise	3.240s	146.665us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	5.910s	769.719us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	8.380s	861.593us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.190s	567.117us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.600s	2.910ms	1	1	100.00
		i2c_target_nack_txstretch	2.350s	1.069ms	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.370s	936.236us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.370s	2.037ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.820s	40.147us	1	1	100.00
V2	intr_test	i2c_intr_test	1.770s	21.957us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.230s	414.157us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.230s	414.157us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.580s	23.591us	1	1	100.00
		i2c_csr_rw	1.810s	20.467us	1	1	100.00
		i2c_csr_aliasing	3.010s	432.498us	1	1	100.00
		i2c_same_csr_outstanding	1.750s	34.319us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.580s	23.591us	1	1	100.00
		i2c_csr_rw	1.810s	20.467us	1	1	100.00
		i2c_csr_aliasing	3.010s	432.498us	1	1	100.00
		i2c_same_csr_outstanding	1.750s	34.319us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.940s	77.302us	1	1	100.00
		i2c_sec_cm	1.730s	223.305us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.940s	77.302us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	4.080s	696.992us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.770s	40.738us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	15.100s	2.218ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.105376688950178992947989093798539483501958035096918053557840403443182874059781
      Line 206, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 21932889449 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @6453858
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.26992969043501202353391314303956921459613029365133271552286376493697242397974
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  40737805 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 115 [0x73])
        UVM_INFO @  40737805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.109165255346353418569229604343781154815898838479888165695719576962672565187781
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10033685754 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10033685754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:907) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.5038997939134782122081131602312074359258998421637988237005831674024380426906
      Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 696991545 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 696991545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:811) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.97883909753483802106080694066616065451508158965225355109985749866437490604583
      Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2217690621 ps: (cip_base_vseq.sv:811) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2217690621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.4572429639350973007868074128345909284647407857981362148422433662427718162245
      Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  46154019 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.90207977453896813228761067958967592020419601880250250346704276171649584876645
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 1068616916 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 1068616916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---