KMAC/MASKED Simulation Results

Wednesday April 16 2025 17:02:56 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	20.970s	757.550us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.780s	96.743us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.890s	118.307us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.360s	573.917us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.140s	792.394us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.680s	50.639us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.890s	118.307us	1	1	100.00
		kmac_csr_aliasing	4.140s	792.394us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.490s	21.002us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.070s	173.073us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	36.809m	106.634ms	1	1	100.00
V2	burst_write	kmac_burst_write	16.736m	69.294ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	29.548m	678.284ms	1	1	100.00
		kmac_test_vectors_sha3_256	23.644m	238.818ms	1	1	100.00
		kmac_test_vectors_sha3_384	22.466m	90.051ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.420s	3.053ms	1	1	100.00
		kmac_test_vectors_shake_128	1.979m	23.806ms	1	1	100.00
		kmac_test_vectors_shake_256	23.198m	34.576ms	1	1	100.00
		kmac_test_vectors_kmac	3.420s	193.012us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.450s	1.045ms	1	1	100.00
V2	sideload	kmac_sideload	5.126m	17.820ms	1	1	100.00
V2	app	kmac_app	2.957m	39.219ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.960m	36.443ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	25.860s	18.422ms	1	1	100.00
V2	error	kmac_error	1.877m	18.554ms	1	1	100.00
V2	key_error	kmac_key_error	10.580s	2.991ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	7.890s	830.765us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	35.140s	4.054ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	28.050s	1.357ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	55.150s	14.113ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.950s	124.344us	1	1	100.00
V2	stress_all	kmac_stress_all	15.606m	147.991ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.660s	49.485us	1	1	100.00
V2	alert_test	kmac_alert_test	1.720s	42.303us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.620s	71.145us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.620s	71.145us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.780s	96.743us	1	1	100.00
		kmac_csr_rw	1.890s	118.307us	1	1	100.00
		kmac_csr_aliasing	4.140s	792.394us	1	1	100.00
		kmac_same_csr_outstanding	3.440s	357.110us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.780s	96.743us	1	1	100.00
		kmac_csr_rw	1.890s	118.307us	1	1	100.00
		kmac_csr_aliasing	4.140s	792.394us	1	1	100.00
		kmac_same_csr_outstanding	3.440s	357.110us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.090s	78.048us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.090s	78.048us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.090s	78.048us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.090s	78.048us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.650s	338.352us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.307m	8.529ms	1	1	100.00
		kmac_tl_intg_err	1.960s	536.523us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.960s	536.523us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.950s	124.344us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	20.970s	757.550us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.126m	17.820ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.090s	78.048us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.307m	8.529ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.307m	8.529ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.307m	8.529ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	20.970s	757.550us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.950s	124.344us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.307m	8.529ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.215m	4.704ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	20.970s	757.550us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	49.450s	2.758ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.13588133372786146904416283996142802975268569741125451322897048671867563272647
      Line 90, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
        UVM_ERROR @ 536523045 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
        UVM_INFO @ 536523045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---