KMAC/UNMASKED Simulation Results

Wednesday April 16 2025 17:02:56 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	30.130s	3.943ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.080s	49.887us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.740s	56.931us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.610s	1.451ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.610s	1.037ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.730s	255.479us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.740s	56.931us	1	1	100.00
		kmac_csr_aliasing	7.610s	1.037ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.790s	12.941us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.070s	51.568us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	2.754m	18.967ms	1	1	100.00
V2	burst_write	kmac_burst_write	10.338m	57.329ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	25.100s	617.924us	1	1	100.00
		kmac_test_vectors_sha3_256	23.360s	584.950us	1	1	100.00
		kmac_test_vectors_sha3_384	15.620s	427.053us	1	1	100.00
		kmac_test_vectors_sha3_512	14.510s	1.084ms	1	1	100.00
		kmac_test_vectors_shake_128	2.005m	26.745ms	1	1	100.00
		kmac_test_vectors_shake_256	25.600m	357.472ms	1	1	100.00
		kmac_test_vectors_kmac	2.840s	166.661us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.540s	99.533us	1	1	100.00
V2	sideload	kmac_sideload	2.470m	16.410ms	1	1	100.00
V2	app	kmac_app	10.170s	1.713ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	35.750s	22.131ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.252m	55.814ms	1	1	100.00
V2	error	kmac_error	2.996m	11.110ms	1	1	100.00
V2	key_error	kmac_key_error	5.140s	1.005ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.459m	10.102ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	32.410s	2.283ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	9.480s	1.908ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	37.800s	8.883ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.950s	52.679us	1	1	100.00
V2	stress_all	kmac_stress_all	8.402m	97.681ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.720s	13.849us	1	1	100.00
V2	alert_test	kmac_alert_test	1.620s	20.578us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.280s	64.072us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.280s	64.072us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.080s	49.887us	1	1	100.00
		kmac_csr_rw	1.740s	56.931us	1	1	100.00
		kmac_csr_aliasing	7.610s	1.037ms	1	1	100.00
		kmac_same_csr_outstanding	2.070s	22.214us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.080s	49.887us	1	1	100.00
		kmac_csr_rw	1.740s	56.931us	1	1	100.00
		kmac_csr_aliasing	7.610s	1.037ms	1	1	100.00
		kmac_same_csr_outstanding	2.070s	22.214us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.060s	148.637us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.060s	148.637us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.060s	148.637us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.060s	148.637us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.470s	88.759us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	43.500s	5.644ms	1	1	100.00
		kmac_tl_intg_err	3.980s	162.104us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.980s	162.104us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.950s	52.679us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	30.130s	3.943ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.470m	16.410ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.060s	148.637us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	43.500s	5.644ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	43.500s	5.644ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	43.500s	5.644ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	30.130s	3.943ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.950s	52.679us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	43.500s	5.644ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.877m	9.969ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	30.130s	3.943ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	41.630s	1.280ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.75136843189370701941723926130761169782275096692089725750484664897593804102284
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10102254968 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd7799000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
        UVM_INFO @ 10102254968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.87222200257361456064148612200944624059271347585150705972972822034883597318331
      Line 110, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1280190831 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1280190831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---