d6a1303| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 35.000s | 11.887ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 3.000s | 39.795us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 4.000s | 29.656us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 40.926us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 3.000s | 54.751us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 3.000s | 980.783ns | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 4.000s | 29.656us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 3.000s | 54.751us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 1.283m | 124.295ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 25.000s | 1.055ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 24.000s | 987.991us | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 3.000s | 64.514us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 4.000s | 3.673us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 4.000s | 3.673us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 3.000s | 39.795us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 29.656us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 3.000s | 54.751us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 59.495us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 3.000s | 39.795us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 29.656us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 3.000s | 54.751us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 59.495us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 4.000s | 15.320us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 3.000s | 47.994us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.14514460651744975861188572601659288224813668917266343250115625547800241887141
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 3673119 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xd2dcccd0 a_data = 0x4b721023 a_mask = 0x0 a_size = 0x3 a_param = 0x0 a_source = 0x7e a_opcode = PutPartialData a_user = 0x27bdb d_data = 0x1eb15543 d_size = 0x3 d_param = 0x0 d_source = 0xa d_opcode = AccessAck d_error = 0 d_user = 10110100111010 d_sink = 1 req_abort_after_a_valid_len = 1 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 3673119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.71321487905938401727464984124306208567872346129278436809075869915680255985742
Line 88, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 47993671 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x8cb35f2c a_data = 0x26b433a8 a_mask = 0x1 a_size = 0x2 a_param = 0x0 a_source = 0x5b a_opcode = Get a_user = 0x24f35 d_data = 0xca8ce2dd d_size = 0x0 d_param = 0x0 d_source = 0x35 d_opcode = AccessAck d_error = 0 d_user = 11110111100010 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 47993671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.34480411972652966468679995473209932787938756282840717894648642043367721231066
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 980783 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x391f8718 a_data = 0x1f6419d2 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0x97 a_opcode = PutFullData a_user = 0x18974 d_data = 0x2ad76841 d_size = 0x2 d_param = 0x0 d_source = 0xd3 d_opcode = AccessAckData d_error = 0 d_user = 11001011000011 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 980783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---