ROM_CTRL/32KB Simulation Results

Wednesday April 16 2025 17:02:56 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.940s 142.924us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.770s 1.621ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 3.980s 242.757us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.900s 165.234us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.960s 546.947us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.830s 143.794us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 3.980s 242.757us 1 1 100.00
rom_ctrl_csr_aliasing 6.960s 546.947us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.270s 295.085us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.240s 125.525us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.120s 600.679us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 19.170s 4.272ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 8.390s 316.247us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.350s 556.085us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 10.280s 133.692us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 10.280s 133.692us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.770s 1.621ms 1 1 100.00
rom_ctrl_csr_rw 3.980s 242.757us 1 1 100.00
rom_ctrl_csr_aliasing 6.960s 546.947us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.010s 553.796us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.770s 1.621ms 1 1 100.00
rom_ctrl_csr_rw 3.980s 242.757us 1 1 100.00
rom_ctrl_csr_aliasing 6.960s 546.947us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.010s 553.796us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 50.710s 3.152ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 17.440s 3.877ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.719m 1.058ms 1 1 100.00
rom_ctrl_tl_intg_err 22.530s 218.039us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.719m 1.058ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.719m 1.058ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 50.710s 3.152ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 50.710s 3.152ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 50.710s 3.152ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 50.710s 3.152ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 50.710s 3.152ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.719m 1.058ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.719m 1.058ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.940s 142.924us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.940s 142.924us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.940s 142.924us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 22.530s 218.039us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 50.710s 3.152ms 1 1 100.00
rom_ctrl_kmac_err_chk 8.390s 316.247us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 50.710s 3.152ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 50.710s 3.152ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 50.710s 3.152ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 17.440s 3.877ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.719m 1.058ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 36.710s 5.928ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00