ROM_CTRL/64KB Simulation Results

Wednesday April 16 2025 17:02:56 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.790s 3.471ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 10.230s 1.702ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.930s 1.065ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.930s 533.365us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.310s 1.067ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 9.990s 2.067ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.930s 1.065ms 1 1 100.00
rom_ctrl_csr_aliasing 7.310s 1.067ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 10.290s 297.600us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.930s 261.779us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.800s 1.465ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 18.600s 2.357ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.360s 2.795ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 8.120s 651.292us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 10.850s 290.996us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 10.850s 290.996us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 10.230s 1.702ms 1 1 100.00
rom_ctrl_csr_rw 7.930s 1.065ms 1 1 100.00
rom_ctrl_csr_aliasing 7.310s 1.067ms 1 1 100.00
rom_ctrl_same_csr_outstanding 6.810s 213.421us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 10.230s 1.702ms 1 1 100.00
rom_ctrl_csr_rw 7.930s 1.065ms 1 1 100.00
rom_ctrl_csr_aliasing 7.310s 1.067ms 1 1 100.00
rom_ctrl_same_csr_outstanding 6.810s 213.421us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.910m 3.789ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 33.440s 1.078ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.207m 1.315ms 1 1 100.00
rom_ctrl_tl_intg_err 36.700s 309.767us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.207m 1.315ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.207m 1.315ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.910m 3.789ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.910m 3.789ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.910m 3.789ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.910m 3.789ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.910m 3.789ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.207m 1.315ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.207m 1.315ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.790s 3.471ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.790s 3.471ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.790s 3.471ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 36.700s 309.767us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.910m 3.789ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.360s 2.795ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.910m 3.789ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.910m 3.789ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.910m 3.789ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 33.440s 1.078ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.207m 1.315ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.369m 8.379ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00