RV_TIMER Simulation Results

Wednesday April 16 2025 17:02:56 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.768m	268.146ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.630s	36.348us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.510s	31.570us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.350s	91.293us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.670s	64.992us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.850s	85.365us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.510s	31.570us	1	1	100.00
		rv_timer_csr_aliasing	1.670s	64.992us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	10.729m	156.700ms	1	1	100.00
V2	disabled	rv_timer_disabled	1.801m	110.976ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	51.050s	50.053ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	51.050s	50.053ms	1	1	100.00
V2	stress	rv_timer_stress_all	12.040m	1.224s	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.370s	32.405us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.230s	498.062us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.230s	498.062us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.630s	36.348us	1	1	100.00
		rv_timer_csr_rw	1.510s	31.570us	1	1	100.00
		rv_timer_csr_aliasing	1.670s	64.992us	1	1	100.00
		rv_timer_same_csr_outstanding	1.810s	53.440us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.630s	36.348us	1	1	100.00
		rv_timer_csr_rw	1.510s	31.570us	1	1	100.00
		rv_timer_csr_aliasing	1.670s	64.992us	1	1	100.00
		rv_timer_same_csr_outstanding	1.810s	53.440us	1	1	100.00
V2		TOTAL			7	7	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.940s	244.867us	1	1	100.00
		rv_timer_tl_intg_err	1.770s	278.343us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.770s	278.343us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	18.370s	20.245ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			15	16	93.75

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:907) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.98144129835381082809162465231280339621170557628852532021896637250626123806422
      Line 136, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20244624773 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10009 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 20244624773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---