SPI_DEVICE/1R1W Simulation Results

Wednesday April 16 2025 17:02:56 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.074m	20.672ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.700s	40.973us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.130s	269.980us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.480s	8.210ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.940s	1.284ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.510s	602.190us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.130s	269.980us	1	1	100.00
		spi_device_csr_aliasing	16.940s	1.284ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.510s	27.687us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.290s	40.707us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.690s	51.068us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.600s	2.705us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.610s	1.585us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	3.960s	529.879us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.960s	529.879us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.530s	310.603us	1	1	100.00
		spi_device_tpm_sts_read	1.870s	54.061us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	5.550s	2.331ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.180s	38.541ms	1	1	100.00
		spi_device_flash_all	14.730s	3.245ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.310s	199.979us	1	1	100.00
		spi_device_flash_all	14.730s	3.245ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.310s	199.979us	1	1	100.00
		spi_device_flash_all	14.730s	3.245ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	14.730s	3.245ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.560s	278.412us	1	1	100.00
		spi_device_flash_all	14.730s	3.245ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.560s	278.412us	1	1	100.00
		spi_device_flash_all	14.730s	3.245ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.560s	278.412us	1	1	100.00
		spi_device_flash_all	14.730s	3.245ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.560s	278.412us	1	1	100.00
		spi_device_flash_all	14.730s	3.245ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.560s	278.412us	1	1	100.00
		spi_device_flash_all	14.730s	3.245ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	14.890s	17.186ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	7.660s	3.805ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	7.660s	3.805ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	7.660s	3.805ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.580s	31.504us	1	1	100.00
		spi_device_read_buffer_direct	6.600s	1.969ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	7.660s	3.805ms	1	1	100.00
		spi_device_flash_all	14.730s	3.245ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	14.730s	3.245ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	14.730s	3.245ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.450s	327.225us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.450s	327.225us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.074m	20.672ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.434m	21.374ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.099m	10.982ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.570s	25.529us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.550s	19.150us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.020s	116.830us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.020s	116.830us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.700s	40.973us	1	1	100.00
		spi_device_csr_rw	2.130s	269.980us	1	1	100.00
		spi_device_csr_aliasing	16.940s	1.284ms	1	1	100.00
		spi_device_same_csr_outstanding	3.940s	212.529us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.700s	40.973us	1	1	100.00
		spi_device_csr_rw	2.130s	269.980us	1	1	100.00
		spi_device_csr_aliasing	16.940s	1.284ms	1	1	100.00
		spi_device_same_csr_outstanding	3.940s	212.529us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.910s	109.071us	1	1	100.00
		spi_device_tl_intg_err	10.100s	566.239us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.100s	566.239us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.896m	36.948ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.92353799061142507532170438887956609599025726824135871275926318667646642155710
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1705128 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[84])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1705128 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1705128 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[980])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.51279194557658527261600662347752077956623708539520845445475340840268968401287
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1073789 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1073789 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1149789 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcb616e [110010110110000101101110] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1149789 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0xcb616e [110010110110000101101110] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])