SPI_HOST Simulation Results

Wednesday April 16 2025 17:02:56 UTC

GitHub Revision: `d6a1303`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	24.000s	12.466ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	26.813us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	38.455us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	109.727us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	35.629us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	27.654us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	38.455us	1	1	100.00
		spi_host_csr_aliasing	4.000s	35.629us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	23.820us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	24.217us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	9.000s	30.689us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	7.000s	82.221us	1	1	100.00
		spi_host_error_cmd	3.000s	16.872us	1	1	100.00
		spi_host_event	25.000s	3.268ms	1	1	100.00
V2	clock_rate	spi_host_speed	15.000s	2.002ms	1	1	100.00
V2	speed	spi_host_speed	15.000s	2.002ms	1	1	100.00
V2	chip_select_timing	spi_host_speed	15.000s	2.002ms	1	1	100.00
V2	sw_reset	spi_host_sw_reset	4.933m	10.035ms	0	1	0.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	633.021us	1	1	100.00
V2	cpol_cpha	spi_host_speed	15.000s	2.002ms	1	1	100.00
V2	full_cycle	spi_host_speed	15.000s	2.002ms	1	1	100.00
V2	duplex	spi_host_smoke	24.000s	12.466ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	24.000s	12.466ms	1	1	100.00
V2	stress_all	spi_host_stress_all	1.167m	8.981ms	1	1	100.00
V2	spien	spi_host_spien	8.000s	509.613us	1	1	100.00
V2	stall	spi_host_status_stall	5.000s	209.399us	0	1	0.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	149.576us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	7.000s	82.221us	1	1	100.00
V2	alert_test	spi_host_alert_test	5.000s	24.154us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	99.900us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	56.685us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	56.685us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	26.813us	1	1	100.00
		spi_host_csr_rw	4.000s	38.455us	1	1	100.00
		spi_host_csr_aliasing	4.000s	35.629us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	21.763us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	26.813us	1	1	100.00
		spi_host_csr_rw	4.000s	38.455us	1	1	100.00
		spi_host_csr_aliasing	4.000s	35.629us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	21.763us	1	1	100.00
V2		TOTAL			13	15	86.67
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	182.807us	1	1	100.00
		spi_host_sec_cm	4.000s	66.981us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	182.807us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	30.683m	100.004ms	0	1	0.00
		TOTAL			23	26	88.46

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 0.spi_host_upper_range_clkdiv.100070298196403005153439858150696291720007509342085756506292666741576631082592
    Line 161, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100004330955 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8edd8ad4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
  UVM_INFO @ 100004330955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=37) has 1 failures:
- Test spi_host_sw_reset has 1 failures.
  - 0.spi_host_sw_reset.2917740383413058331220179285867454661970925352244048163241660410937594760766
    Line 253, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_sw_reset/latest/run.log
```
  UVM_FATAL @ 10034637978 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe0b9aed4, Comparison=CompareOpEq, exp_data=0x0, call_count=37)
  UVM_INFO @ 10034637978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

Test spi_host_status_stall has 1 failures.

0.spi_host_status_stall.7804787483401765749589874946871488072097691968961226010980533422860164606155
Line 732, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 209398601 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 209398601 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=209399000 ps
  UVM_INFO @ 209398601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---