SRAM_CTRL/MAIN Simulation Results

Wednesday April 16 2025 17:02:56 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	12.560s	3.515ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.620s	21.064us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.560s	25.154us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.550s	487.958us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.640s	18.931us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.040s	403.630us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.560s	25.154us	1	1	100.00
		sram_ctrl_csr_aliasing	1.640s	18.931us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.593m	37.515ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.783m	27.297ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	11.889m	18.271ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.609m	13.309ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	28.225m	599.755ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.889m	42.555ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	50.040s	14.373ms	1	1	100.00
V2	executable	sram_ctrl_executable	1.411m	4.150ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	46.940s	7.995ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.559m	6.232ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	39.250s	784.066us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	26.790s	2.968ms	1	1	100.00
		sram_ctrl_throughput_w_readback	8.540s	4.761ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	1.952m	15.420ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.230s	351.809us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	32.751m	381.143ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.650s	12.370us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.490s	81.839us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.490s	81.839us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.620s	21.064us	1	1	100.00
		sram_ctrl_csr_rw	1.560s	25.154us	1	1	100.00
		sram_ctrl_csr_aliasing	1.640s	18.931us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.560s	57.647us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.620s	21.064us	1	1	100.00
		sram_ctrl_csr_rw	1.560s	25.154us	1	1	100.00
		sram_ctrl_csr_aliasing	1.640s	18.931us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.560s	57.647us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	30.360s	7.249ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.580s	3.528us	0	1	0.00
		sram_ctrl_tl_intg_err	2.230s	241.356us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.580s	3.528us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.230s	241.356us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.952m	15.420ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.952m	15.420ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.560s	25.154us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.411m	4.150ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.411m	4.150ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.411m	4.150ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	50.040s	14.373ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.500s	693.552us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	30.360s	7.249ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	7.300s	697.940us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	12.560s	3.515ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	12.560s	3.515ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.411m	4.150ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.580s	3.528us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	50.040s	14.373ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.580s	3.528us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.580s	3.528us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	12.560s	3.515ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.580s	3.528us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	21.410s	4.475ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.110264069408526391984624576751329102740668448588476225179704619185259805108524
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 693552341 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 693552341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.79195111036396549980658573712525100429998845373679156110652542137663873684443
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3528279 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3528279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---