UART Simulation Results

Wednesday April 16 2025 17:02:56 UTC

GitHub Revision: `d6a1303`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	12.080s	5.919ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.380s	57.488us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.630s	48.588us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.380s	473.234us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.700s	474.175us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.720s	19.526us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.630s	48.588us	1	1	100.00
		uart_csr_aliasing	1.700s	474.175us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.263m	219.865ms	1	1	100.00
V2	parity	uart_smoke	12.080s	5.919ms	1	1	100.00
		uart_tx_rx	1.263m	219.865ms	1	1	100.00
V2	parity_error	uart_intr	4.885m	266.369ms	1	1	100.00
		uart_rx_parity_err	29.740s	52.003ms	1	1	100.00
V2	watermark	uart_tx_rx	1.263m	219.865ms	1	1	100.00
		uart_intr	4.885m	266.369ms	1	1	100.00
V2	fifo_full	uart_fifo_full	37.730s	32.427ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	25.910s	22.479ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	54.780s	234.253ms	1	1	100.00
V2	rx_frame_err	uart_intr	4.885m	266.369ms	1	1	100.00
V2	rx_break_err	uart_intr	4.885m	266.369ms	1	1	100.00
V2	rx_timeout	uart_intr	4.885m	266.369ms	1	1	100.00
V2	perf	uart_perf	10.540m	16.041ms	1	1	100.00
V2	sys_loopback	uart_loopback	6.080s	1.954ms	1	1	100.00
V2	line_loopback	uart_loopback	6.080s	1.954ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.133m	64.488ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.500s	429.621us	1	1	100.00
V2	tx_overide	uart_tx_ovrd	8.340s	7.357ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	30.310s	5.520ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.097m	62.568ms	1	1	100.00
V2	stress_all	uart_stress_all	1.606m	246.689ms	1	1	100.00
V2	alert_test	uart_alert_test	1.490s	30.359us	1	1	100.00
V2	intr_test	uart_intr_test	1.630s	24.213us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.000s	197.847us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.000s	197.847us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.380s	57.488us	1	1	100.00
		uart_csr_rw	1.630s	48.588us	1	1	100.00
		uart_csr_aliasing	1.700s	474.175us	1	1	100.00
		uart_same_csr_outstanding	1.800s	26.240us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.380s	57.488us	1	1	100.00
		uart_csr_rw	1.630s	48.588us	1	1	100.00
		uart_csr_aliasing	1.700s	474.175us	1	1	100.00
		uart_same_csr_outstanding	1.800s	26.240us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.760s	155.532us	1	1	100.00
		uart_tl_intg_err	2.130s	88.423us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.130s	88.423us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	18.690s	3.745ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			26	27	96.30

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:811) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.

has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

0.uart_stress_all_with_rand_reset.58799386652561420456368730119653054476486676449799911745153957677063782876954
Line 106, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2292224356 ps: (cip_base_vseq.sv:811) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2292224356 ps: (cip_base_vseq.sv:815) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 4/5
  UVM_INFO @ 2292324356 ps: (cip_base_vseq.sv:835) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 4/5