CHIP Simulation Results

Wednesday April 16 2025 17:02:56 UTC

GitHub Revision: `d6a1303`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.508m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.508m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.070m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	57.981s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	45.042s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.515m	5.939ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.515m	5.939ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.515m	5.939ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	2.582m		0	1	0.00
		chip_sw_example_manufacturer	29.862s		0	1	0.00
		chip_sw_example_concurrency	4.835m	5.528ms	1	1	100.00
		chip_sw_uart_smoketest_signed	17.834s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.310s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.340s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.340s		0	1	0.00
V1	xbar_smoke	xbar_smoke	16.990s	59.049us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.546m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.154m	8.247ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.199m	5.268ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	11.802s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	17.693s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	51.520s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	17.187s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.640s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.640s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.982m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.782m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.095m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.095m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.571m	4.005ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.129m	4.058ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.325m	7.866ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	13.326s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.598s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	17.843m	21.243ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.441m	5.159ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	20.444m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	20.444m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.468s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	13.911s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	13.911s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	17.289s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.808m	4.558ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.017m	3.914ms	1	1	100.00
		chip_sw_aes_idle	4.125m	4.676ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.750m	4.787ms	1	1	100.00
		chip_sw_kmac_idle	4.307m	4.368ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.331s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	13.470s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	12.249s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	13.237s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	10.742s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.096s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.165s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.397s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.487s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.908s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.298s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.742s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.096s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.165s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.397s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.487s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.908s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.298s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.523s		0	1	0.00
		chip_sw_aes_enc_jitter_en	46.530s	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	50.870s	10.100us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	52.160s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	46.760s	10.300us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.338s		0	1	0.00
		chip_sw_clkmgr_jitter	3.751m	3.567ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.201m	3.562ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	14.233s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	50.780s	10.180us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	46.710s	10.100us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	48.080s	10.220us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	1.046m	10.300us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	45.300s	10.220us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.230s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.968s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.774s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	13.633s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	18.910m	12.738ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.065m	13.799ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	13.911s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	13.909s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.065m	13.799ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	21.335s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	11.418s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	15.049s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	21.776s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.159s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	18.910m	12.738ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.325m	7.866ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	8.696m	20.015ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.686m	8.945ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	20.875m	30.024ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.000m	4.295ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	18.910m	12.738ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	12.712s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.783s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	18.910m	12.738ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	13.229s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	20.875m	30.024ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.912s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.816s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.070s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.505s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	10.700s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.137s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.783s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	12.112s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	14.353s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.112s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.112s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.112s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	7.797m	20.010ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	21.439s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	15.721s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	19.076s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	18.535s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.112s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	8.083m	20.010ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.082m	10.434ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	12.169s		0	1	0.00
		chip_prim_tl_access	19.191m	21.056ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.742s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.096s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.165s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.397s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.487s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.908s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.298s		0	1	0.00
		chip_rv_dm_lc_disabled	17.843m	21.243ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.107m	3.985ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	46.530s	10.400us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.494m	4.573ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.125m	4.676ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.486m	4.411ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	50.870s	10.100us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.750m	4.787ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.558m	4.745ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.745m	5.567ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	46.760s	10.300us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	8.083m	20.010ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.112s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	38.160s	10.280us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.140m	5.921ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.307m	4.368ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.357s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.357s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	11.368s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.643m	4.443ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	13.871s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	8.083m	20.010ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	52.160s	10.240us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	13.891s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	10.523s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.017m	3.914ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.017m	3.914ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.017m	3.914ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.789m	6.051ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.082m	10.434ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.082m	10.434ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.532m	6.409ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.338s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	12.169s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	18.910m	12.738ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.095m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.112s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.789m	6.051ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.083m	20.010ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.532m	6.409ms	0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	4.111m	5.489ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.789m	6.051ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.083m	20.010ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.532m	6.409ms	0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	4.111m	5.489ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.112s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	13.489s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	14.353s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	21.439s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	15.721s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	19.076s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	18.535s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.112s		0	1	0.00
		chip_prim_tl_access	19.191m	21.056ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	19.191m	21.056ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	18.872s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	11.846s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.968s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.523s		0	1	0.00
		chip_sw_aes_enc_jitter_en	46.530s	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	50.870s	10.100us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	52.160s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	46.760s	10.300us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.338s		0	1	0.00
		chip_sw_clkmgr_jitter	3.751m	3.567ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.143m	10.675ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.143m	10.675ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.135m	4.453ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	5.259m	3.576ms	1	1	100.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.076m	4.360ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.647m	6.645ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.016m	4.856ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.670m	5.708ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.111m	5.489ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	8.696m	20.015ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	8.696m	20.015ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.804m	4.816ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.342m	3.425ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.845m	3.815ms	1	1	100.00
		chip_sw_csrng_smoketest	3.413m	3.713ms	1	1	100.00
		chip_sw_gpio_smoketest	3.739m	5.032ms	1	1	100.00
		chip_sw_hmac_smoketest	4.194m	4.459ms	1	1	100.00
		chip_sw_kmac_smoketest	4.086m	5.212ms	1	1	100.00
		chip_sw_otbn_smoketest	4.579m	5.216ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.531m	4.942ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.030m	4.225ms	1	1	100.00
		chip_sw_rv_timer_smoketest	3.933m	4.312ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.778m	2.992ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.048m	5.602ms	1	1	100.00
		chip_sw_uart_smoketest	3.268m	5.916ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	19.309s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	17.834s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.546m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.096s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.236m	4.014ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.613m	4.244ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.196m	4.349ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.001m	4.546ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	35.808s		0	1	0.00
		chip_rv_dm_lc_disabled	17.843m	21.243ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	14.349s		0	1	0.00
		chip_sw_lc_walkthrough_prod	15.830s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	13.024s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.157s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	35.808s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	32.258s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	15.512s		0	1	0.00
		rom_volatile_raw_unlock	10.722s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.766s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.180m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.435m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.994m	4.232ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.994m	4.232ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.340s		0	1	0.00
		chip_same_csr_outstanding	9.570s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.340s		0	1	0.00
		chip_same_csr_outstanding	9.570s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.567m	240.627us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.030s	12.548us	1	1	100.00
		xbar_smoke_large_delays	4.958m	2.617ms	1	1	100.00
		xbar_smoke_slow_rsp	4.839m	1.805ms	1	1	100.00
		xbar_random_zero_delays	51.130s	48.471us	1	1	100.00
		xbar_random_large_delays	26.245m	13.632ms	1	1	100.00
		xbar_random_slow_rsp	19.087m	7.139ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.606m	189.158us	1	1	100.00
		xbar_error_and_unmapped_addr	11.500s	10.849us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	33.990s	34.017us	1	1	100.00
		xbar_error_and_unmapped_addr	11.500s	10.849us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.165m	119.121us	1	1	100.00
		xbar_access_same_device_slow_rsp	7.884m	2.933ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	20.130s	43.081us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	8.412m	1.134ms	1	1	100.00
		xbar_stress_all_with_error	1.189m	215.821us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.782m	97.154us	1	1	100.00
		xbar_stress_all_with_reset_error	16.878m	679.579us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	14.507s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.309s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.881s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.204s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.282s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.436s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.823s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.924s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.242s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	12.395s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.983s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.498s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	13.168s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.257s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.485s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.980s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.490s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.463s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.218s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.245s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	13.402s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.186s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.523s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.503s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	11.672s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.289s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.125s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	11.536s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	11.609s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.608s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	11.606s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.621s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.513s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.565s		0	1	0.00
		rom_e2e_asm_init_dev	11.130s		0	1	0.00
		rom_e2e_asm_init_prod	10.876s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.449s		0	1	0.00
		rom_e2e_asm_init_rma	10.810s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.162s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.960s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.693s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.162s		0	1	0.00
V2		TOTAL			66	205	32.20
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.138m	3.982ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.955m	3.933ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	10.833s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.340s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.176s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.688s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	18.910m	12.738ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	13.728s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	16.568m	12.935ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	14.960s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	10.724s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	10.833s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.340s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.176s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.927s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.000s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.830s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.424m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	18.861m	15.747ms	1	1	100.00
		chip_plic_all_irqs_0	9.105m	6.997ms	1	1	100.00
		chip_plic_all_irqs_10	8.701m	6.204ms	1	1	100.00
		chip_sw_dma_inline_hashing	5.289m	6.052ms	1	1	100.00
		chip_sw_dma_abort	3.787m	4.024ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.671s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.496s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.502s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	12.079s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.804s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.560s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.301s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.867s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.256s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.714s		0	1	0.00
		chip_sw_mbx_smoketest	4.117m	4.688ms	1	1	100.00
		TOTAL			77	247	31.17

Failure Buckets

Job returned non-zero exit code has 143 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.30168535323485913434038484155306382336994482372848124033729089263435587538181
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  DEBUG: /nightly/runs/opentitan/rules/autogen.bzl:452:14: NOTE: stamping is disabled, the chip_info section will use a fixed version string
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (be8557)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (f1c34c)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 138.860s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.80076656408911820540819142474978179037318127660495474787892762587197178774315
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (2ea18b)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 15.244s, Critical Path: 0.05s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.114518876065424954671040851915277582675805576054417657300311318061699619019510
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (f337b6)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 113.705s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.90569566347591847390792619255243064055187709322356046063616230749797695183430
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (e0f752)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 107.436s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.25628519958783911099162427393774273131617494134413081184053998811949726309284
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (9ca6d4)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 96.768s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 138 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.49044202043945643935657871424362711427475889195704814710399548063751023275293
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.32987142987296112118393775332664825346364825058022775263460276924735623597965
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.39939842915570205367091290406396828265409980522879000435309419866058921165388
    Line 406, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.62750927130455740702205806086769721177896340587912756595263006045010905199825
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.5559553988542469069172167134867883803240390576833781841020038876289504242467
    Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.53013484555400222746711805726400732100163311127796946556509341142220344902574
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.66592576121250350639869611790182846111495032065438431083158162369755524588592
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.112112117466845064410212597967327292608628671941292526398999748054132110670117
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 2 failures:
- Test chip_sw_rstmgr_cpu_info has 1 failures.
  - 0.chip_sw_rstmgr_cpu_info.87550225802580429754880287018790850465558037143870537614830713621437721776765
    Line 450, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
```
  UVM_ERROR @ 20014.770612 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20014.770612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aon_timer_irq has 1 failures.
  - 0.chip_sw_aon_timer_irq.39368196712366212836341801602413713613816579561285905922654246731486506861422
    Line 437, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
```
  UVM_ERROR @ 18026.788737 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.788737 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage * key has 2 failures:
- Test chip_sw_keymgr_dpe_key_derivation has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation.85710680323864124827462224190793424123773539039360716174337520920718120955976
    Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log
```
  UVM_FATAL @ 20010.120001 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage 0 key
  UVM_INFO @ 20010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_prod.102517378798481235935089162924417589492045252972488933079239843661446822052397
    Line 429, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
```
  UVM_FATAL @ 20010.360001 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage 0 key
  UVM_INFO @ 20010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.81826835393742836427623558079596483750418828958580315545204121381684479756340
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4005.486193 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'ha24770c4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h1  a_user: 'h2488f  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4005.486193 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.112512297370409648988546356041666422183284604833347562971228349059834498737179
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4057.859030 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h1f74f6d5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h31  a_opcode: 'h0  a_user: 'h26979  d_param: 'h0  d_source: 'h31  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4057.859030 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.58926101899059155571149414355756912222688388728597211967752278464141175989927
    Line 453, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5268.277360 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5268.277360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.55457789114580261874494725197615385779509564114425822503876477731716114117648
    Line 456, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 30024.430942 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 30000000 ns

  UVM_INFO @ 30024.430942 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.100561096327386768989625134604226886544170945609210593340695888995097339209405
    Line 439, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4453.317794 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4453.317794 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.14891347892824732878617465087838367609158669844872613957704116455309505650335
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6645.306512 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6645.306512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.39848157582912386395022654059698124828967556207117798030618586237813267776858
    Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_sram_ctrl_scrambled_access has 1 failures.
  - 0.chip_sw_sram_ctrl_scrambled_access.37006363159530248173317985048035361160031703854868197498664766531481543223150
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access/latest/run.log
```
  UVM_ERROR @ 6408.818140 us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 6408.818140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@35815) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.51513669332283089989914080777467543474551722409478063809473646958467150292492
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 4232.243188 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@35815) { a_addr: 'h1465310  a_data: 'hc0f7d8b4  a_mask: 'h1  a_size: 'h2  a_param: 'h0  a_source: 'h2c  a_opcode: 'h4  a_user: 'h253c7  d_param: 'h0  d_source: 'h2c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4232.243188 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.46545000090711770521763232008429579266512593221979518260685663273166136624353
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.90814614602550142763441636457206537557905140079359090854458486421685540718248
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4024.488382 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4024.488382 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```