AES/UNMASKED Simulation Results

Thursday April 17 2025 17:08:19 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	70.954us	1	1	100.00
V1	smoke	aes_smoke	5.000s	70.721us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	62.346us	1	1	100.00
V1	csr_rw	aes_csr_rw	5.000s	67.892us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	6.000s	151.809us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	129.200us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	59.747us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	67.892us	1	1	100.00
		aes_csr_aliasing	6.000s	129.200us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	5.000s	70.721us	1	1	100.00
		aes_config_error	5.000s	124.914us	1	1	100.00
		aes_stress	5.000s	82.613us	1	1	100.00
V2	key_length	aes_smoke	5.000s	70.721us	1	1	100.00
		aes_config_error	5.000s	124.914us	1	1	100.00
		aes_stress	5.000s	82.613us	1	1	100.00
V2	back2back	aes_stress	5.000s	82.613us	1	1	100.00
		aes_b2b	8.000s	120.431us	1	1	100.00
V2	backpressure	aes_stress	5.000s	82.613us	1	1	100.00
V2	multi_message	aes_smoke	5.000s	70.721us	1	1	100.00
		aes_config_error	5.000s	124.914us	1	1	100.00
		aes_stress	5.000s	82.613us	1	1	100.00
		aes_alert_reset	5.000s	162.792us	1	1	100.00
V2	failure_test	aes_man_cfg_err	4.000s	73.601us	1	1	100.00
		aes_config_error	5.000s	124.914us	1	1	100.00
		aes_alert_reset	5.000s	162.792us	1	1	100.00
V2	trigger_clear_test	aes_clear	5.000s	203.772us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	112.487us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	162.792us	1	1	100.00
V2	stress	aes_stress	5.000s	82.613us	1	1	100.00
V2	sideload	aes_stress	5.000s	82.613us	1	1	100.00
		aes_sideload	5.000s	283.770us	1	1	100.00
V2	deinitialization	aes_deinit	5.000s	114.102us	1	1	100.00
V2	stress_all	aes_stress_all	7.000s	450.812us	1	1	100.00
V2	alert_test	aes_alert_test	4.000s	53.420us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	101.232us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	101.232us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	62.346us	1	1	100.00
		aes_csr_rw	5.000s	67.892us	1	1	100.00
		aes_csr_aliasing	6.000s	129.200us	1	1	100.00
		aes_same_csr_outstanding	5.000s	243.384us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	62.346us	1	1	100.00
		aes_csr_rw	5.000s	67.892us	1	1	100.00
		aes_csr_aliasing	6.000s	129.200us	1	1	100.00
		aes_same_csr_outstanding	5.000s	243.384us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	5.000s	70.343us	1	1	100.00
V2S	fault_inject	aes_fi	5.000s	141.413us	1	1	100.00
		aes_control_fi	4.000s	56.102us	1	1	100.00
		aes_cipher_fi	5.000s	131.240us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	65.868us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	65.868us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	65.868us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	65.868us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	243.001us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	424.568us	1	1	100.00
		aes_tl_intg_err	4.000s	143.360us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	143.360us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	162.792us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	65.868us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	70.721us	1	1	100.00
		aes_stress	5.000s	82.613us	1	1	100.00
		aes_alert_reset	5.000s	162.792us	1	1	100.00
		aes_core_fi	5.000s	70.403us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	65.868us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	59.047us	1	1	100.00
		aes_stress	5.000s	82.613us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	82.613us	1	1	100.00
		aes_sideload	5.000s	283.770us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	59.047us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	59.047us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	59.047us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	59.047us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	59.047us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	82.613us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	82.613us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	141.413us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	141.413us	1	1	100.00
		aes_control_fi	4.000s	56.102us	1	1	100.00
		aes_cipher_fi	5.000s	131.240us	1	1	100.00
		aes_ctr_fi	4.000s	86.233us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	141.413us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	141.413us	1	1	100.00
		aes_control_fi	4.000s	56.102us	1	1	100.00
		aes_cipher_fi	5.000s	131.240us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	5.000s	131.240us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	141.413us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	141.413us	1	1	100.00
		aes_control_fi	4.000s	56.102us	1	1	100.00
		aes_ctr_fi	4.000s	86.233us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	141.413us	1	1	100.00
		aes_control_fi	4.000s	56.102us	1	1	100.00
		aes_cipher_fi	5.000s	131.240us	1	1	100.00
		aes_ctr_fi	4.000s	86.233us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	162.792us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	141.413us	1	1	100.00
		aes_control_fi	4.000s	56.102us	1	1	100.00
		aes_cipher_fi	5.000s	131.240us	1	1	100.00
		aes_ctr_fi	4.000s	86.233us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	141.413us	1	1	100.00
		aes_control_fi	4.000s	56.102us	1	1	100.00
		aes_cipher_fi	5.000s	131.240us	1	1	100.00
		aes_ctr_fi	4.000s	86.233us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	141.413us	1	1	100.00
		aes_control_fi	4.000s	56.102us	1	1	100.00
		aes_ctr_fi	4.000s	86.233us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	141.413us	1	1	100.00
		aes_control_fi	4.000s	56.102us	1	1	100.00
		aes_cipher_fi	5.000s	131.240us	1	1	100.00
V2S		TOTAL			11	11	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	8.000s	455.936us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			31	32	96.88

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.111564876328691909292899386925371991756772634249263944528680139734101880411808
      Line 439, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 455935502 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 455895502 PS)
              ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                         |
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 455935502 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 455895502 PS)
        UVM_ERROR @ 455935502 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut