DMA Simulation Results

Thursday April 17 2025 17:08:19 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	9.000s	1.141ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	11.000s	1.754ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	1.124ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	90.045us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	114.296us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	15.000s	4.526ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	461.534us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	29.877us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	114.296us	1	1	100.00
		dma_csr_aliasing	6.000s	461.534us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.683m	7.337ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	4.067m	22.942ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	1.583m	9.091ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	7.333m	578.635ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	4.067m	22.942ms	1	1	100.00
V2	dma_abort	dma_abort	25.000s	1.769ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	4.033m	21.422ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	13.868us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	4.000s	43.170us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	4.000s	43.170us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	90.045us	1	1	100.00
		dma_csr_rw	4.000s	114.296us	1	1	100.00
		dma_csr_aliasing	6.000s	461.534us	1	1	100.00
		dma_same_csr_outstanding	5.000s	191.104us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	90.045us	1	1	100.00
		dma_csr_rw	4.000s	114.296us	1	1	100.00
		dma_csr_aliasing	6.000s	461.534us	1	1	100.00
		dma_same_csr_outstanding	5.000s	191.104us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	30.000s	184.805us	1	1	100.00
		dma_generic_stress	7.333m	578.635ms	1	1	100.00
		dma_handshake_stress	4.067m	22.942ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	112.693us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	2.267m	23.383ms	1	1	100.00
		dma_longer_transfer	25.000s	4.987ms	1	1	100.00
		TOTAL			21	21	100.00