EDN Simulation Results

Thursday April 17 2025 17:08:19 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.740s	25.182us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.630s	39.082us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.670s	15.664us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.510s	1.145ms	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.760s	103.623us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.660s	48.094us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.670s	15.664us	1	1	100.00
		edn_csr_aliasing	1.760s	103.623us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	4.510s	777.659us	1	1	100.00
V2	csrng_commands	edn_genbits	4.510s	777.659us	1	1	100.00
V2	genbits	edn_genbits	4.510s	777.659us	1	1	100.00
V2	interrupts	edn_intr	1.770s	32.748us	1	1	100.00
V2	alerts	edn_alert	1.870s	60.561us	1	1	100.00
V2	errs	edn_err	1.860s	22.169us	1	1	100.00
V2	disable	edn_disable	1.640s	21.010us	1	1	100.00
		edn_disable_auto_req_mode	1.990s	47.342us	1	1	100.00
V2	stress_all	edn_stress_all	2.740s	191.511us	1	1	100.00
V2	intr_test	edn_intr_test	1.610s	75.471us	1	1	100.00
V2	alert_test	edn_alert_test	1.570s	33.252us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.580s	275.074us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.580s	275.074us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.630s	39.082us	1	1	100.00
		edn_csr_rw	1.670s	15.664us	1	1	100.00
		edn_csr_aliasing	1.760s	103.623us	1	1	100.00
		edn_same_csr_outstanding	2.070s	32.889us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.630s	39.082us	1	1	100.00
		edn_csr_rw	1.670s	15.664us	1	1	100.00
		edn_csr_aliasing	1.760s	103.623us	1	1	100.00
		edn_same_csr_outstanding	2.070s	32.889us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	7.520s	1.155ms	1	1	100.00
		edn_tl_intg_err	2.270s	67.236us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.850s	62.468us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.870s	60.561us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.520s	1.155ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.520s	1.155ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.520s	1.155ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.520s	1.155ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.870s	60.561us	1	1	100.00
		edn_sec_cm	7.520s	1.155ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.870s	60.561us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.270s	67.236us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	47.800s	11.780ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00