HMAC Simulation Results

Thursday April 17 2025 17:08:19 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 3.100s 1.884ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.680s 26.984us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.860s 19.419us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 9.940s 1.883ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.520s 723.448us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.150s 35.120us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.860s 19.419us 1 1 100.00
hmac_csr_aliasing 6.520s 723.448us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 10.540s 908.202us 1 1 100.00
V2 back_pressure hmac_back_pressure 58.180s 18.036ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 2.959m 23.970ms 1 1 100.00
hmac_test_sha384_vectors 7.455m 28.661ms 1 1 100.00
hmac_test_sha512_vectors 6.137m 10.359ms 1 1 100.00
hmac_test_hmac256_vectors 11.880s 324.831us 1 1 100.00
hmac_test_hmac384_vectors 10.400s 961.161us 1 1 100.00
hmac_test_hmac512_vectors 10.180s 582.083us 1 1 100.00
V2 burst_wr hmac_burst_wr 8.020s 1.846ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 13.345m 23.484ms 1 1 100.00
V2 error hmac_error 33.710s 3.700ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.654m 46.382ms 1 1 100.00
V2 save_and_restore hmac_smoke 3.100s 1.884ms 1 1 100.00
hmac_long_msg 10.540s 908.202us 1 1 100.00
hmac_back_pressure 58.180s 18.036ms 1 1 100.00
hmac_datapath_stress 13.345m 23.484ms 1 1 100.00
hmac_burst_wr 8.020s 1.846ms 1 1 100.00
hmac_stress_all 14.451m 84.060ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 3.100s 1.884ms 1 1 100.00
hmac_long_msg 10.540s 908.202us 1 1 100.00
hmac_back_pressure 58.180s 18.036ms 1 1 100.00
hmac_datapath_stress 13.345m 23.484ms 1 1 100.00
hmac_wipe_secret 1.654m 46.382ms 1 1 100.00
hmac_test_sha256_vectors 2.959m 23.970ms 1 1 100.00
hmac_test_sha384_vectors 7.455m 28.661ms 1 1 100.00
hmac_test_sha512_vectors 6.137m 10.359ms 1 1 100.00
hmac_test_hmac256_vectors 11.880s 324.831us 1 1 100.00
hmac_test_hmac384_vectors 10.400s 961.161us 1 1 100.00
hmac_test_hmac512_vectors 10.180s 582.083us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 3.100s 1.884ms 1 1 100.00
hmac_long_msg 10.540s 908.202us 1 1 100.00
hmac_back_pressure 58.180s 18.036ms 1 1 100.00
hmac_datapath_stress 13.345m 23.484ms 1 1 100.00
hmac_burst_wr 8.020s 1.846ms 1 1 100.00
hmac_error 33.710s 3.700ms 1 1 100.00
hmac_wipe_secret 1.654m 46.382ms 1 1 100.00
hmac_test_sha256_vectors 2.959m 23.970ms 1 1 100.00
hmac_test_sha384_vectors 7.455m 28.661ms 1 1 100.00
hmac_test_sha512_vectors 6.137m 10.359ms 1 1 100.00
hmac_test_hmac256_vectors 11.880s 324.831us 1 1 100.00
hmac_test_hmac384_vectors 10.400s 961.161us 1 1 100.00
hmac_test_hmac512_vectors 10.180s 582.083us 1 1 100.00
hmac_stress_all 14.451m 84.060ms 1 1 100.00
V2 stress_all hmac_stress_all 14.451m 84.060ms 1 1 100.00
V2 alert_test hmac_alert_test 1.660s 37.502us 1 1 100.00
V2 intr_test hmac_intr_test 1.510s 48.265us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.690s 69.470us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.690s 69.470us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.680s 26.984us 1 1 100.00
hmac_csr_rw 1.860s 19.419us 1 1 100.00
hmac_csr_aliasing 6.520s 723.448us 1 1 100.00
hmac_same_csr_outstanding 2.180s 48.204us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.680s 26.984us 1 1 100.00
hmac_csr_rw 1.860s 19.419us 1 1 100.00
hmac_csr_aliasing 6.520s 723.448us 1 1 100.00
hmac_same_csr_outstanding 2.180s 48.204us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.170s 240.092us 1 1 100.00
hmac_tl_intg_err 2.180s 247.710us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.180s 247.710us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 3.100s 1.884ms 1 1 100.00
V3 stress_reset hmac_stress_reset 2.740s 267.217us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.153m 8.018ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.860s 11.354us 1 1 100.00
TOTAL 28 28 100.00