I2C Simulation Results

Thursday April 17 2025 17:08:19 UTC

GitHub Revision: `91d1222`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	21.460s	7.523ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	28.230s	1.331ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.590s	20.161us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.600s	29.992us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.110s	427.727us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.380s	688.186us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.880s	130.978us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.600s	29.992us	1	1	100.00
		i2c_csr_aliasing	2.380s	688.186us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.280s	515.819us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	4.169m	13.769ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	48.680s	6.314ms	1	1	100.00
V2	host_override	i2c_host_override	1.560s	67.521us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.228m	13.750ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.130m	9.888ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.870s	121.952us	1	1	100.00
		i2c_host_fifo_fmt_empty	14.380s	2.099ms	1	1	100.00
		i2c_host_fifo_reset_rx	4.460s	952.140us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	58.390s	7.452ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	6.890s	5.109ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.570s	161.183us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.080s	9.911ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	5.729m	24.493ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.200s	530.223us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	27.960s	977.751us	1	1	100.00
		i2c_target_intr_smoke	4.390s	938.783us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.910s	173.436us	1	1	100.00
		i2c_target_fifo_reset_tx	1.780s	203.516us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	12.790s	20.115ms	1	1	100.00
		i2c_target_stress_rd	27.960s	977.751us	1	1	100.00
		i2c_target_intr_stress_wr	22.110s	15.963ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.230s	1.333ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	13.270s	10.002ms	0	1	0.00
V2	bad_address	i2c_target_bad_addr	5.270s	1.210ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.830s	714.462us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.610s	625.802us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.700s	253.207us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	48.680s	6.314ms	1	1	100.00
		i2c_host_perf_precise	1.850s	47.051us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	6.890s	5.109ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.720s	90.606us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.090s	1.918ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.600s	981.660us	1	1	100.00
		i2c_target_nack_txstretch	2.390s	425.355us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.640s	1.366ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.390s	878.741us	1	1	100.00
V2	alert_test	i2c_alert_test	1.460s	17.518us	1	1	100.00
V2	intr_test	i2c_intr_test	1.520s	18.068us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.610s	124.389us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.610s	124.389us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.590s	20.161us	1	1	100.00
		i2c_csr_rw	1.600s	29.992us	1	1	100.00
		i2c_csr_aliasing	2.380s	688.186us	1	1	100.00
		i2c_same_csr_outstanding	1.800s	132.638us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.590s	20.161us	1	1	100.00
		i2c_csr_rw	1.600s	29.992us	1	1	100.00
		i2c_csr_aliasing	2.380s	688.186us	1	1	100.00
		i2c_same_csr_outstanding	1.800s	132.638us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.440s	95.050us	1	1	100.00
		i2c_sec_cm	1.550s	73.212us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.440s	95.050us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	10.850s	1.781ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.170s	129.715us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	7.640s	3.880ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:924) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.35107619702138176540389615291291909087350838659480774805380828206891547131139
    Line 96, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1780704384 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1780704384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.76269405394008567014044274231504286339831582700046087902521111650269868928758
    Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3880223703 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3880223703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.108225403657371943883562700207591481204808354397463426453343731484059379107011
Line 125, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 13768553022 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2427788

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 1 failures:
- Test i2c_target_stretch has 1 failures.
  - 0.i2c_target_stretch.22806104840896850320488983496397083197295775087218744191509513275202698647392
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10001509390 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10001509390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.41449660617220013327791313051450464681880995901917466316992594265025821321449
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 129715212 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 91 [0x5b])
  UVM_INFO @ 129715212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 0.i2c_host_mode_toggle.74929267218609538808615007489083881058318201980065764559894529622734862714595
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 161183275 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x230d3f94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 161183275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```