KEYMGR_DPE Simulation Results

Thursday April 17 2025 17:08:19 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	17.090s	932.527us	1	1	100.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	2.130s	19.385us	1	1	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.980s	14.548us	1	1	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	4.420s	345.953us	1	1	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	5.180s	314.696us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	2.410s	30.696us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.980s	14.548us	1	1	100.00
		keymgr_dpe_csr_aliasing	5.180s	314.696us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	intr_test	keymgr_dpe_intr_test	1.620s	9.917us	1	1	100.00
V2	alert_test	keymgr_dpe_alert_test	1.850s	49.541us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	2.480s	27.886us	1	1	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	2.480s	27.886us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	2.130s	19.385us	1	1	100.00
		keymgr_dpe_csr_rw	1.980s	14.548us	1	1	100.00
		keymgr_dpe_csr_aliasing	5.180s	314.696us	1	1	100.00
		keymgr_dpe_same_csr_outstanding	3.040s	134.623us	1	1	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	2.130s	19.385us	1	1	100.00
		keymgr_dpe_csr_rw	1.980s	14.548us	1	1	100.00
		keymgr_dpe_csr_aliasing	5.180s	314.696us	1	1	100.00
		keymgr_dpe_same_csr_outstanding	3.040s	134.623us	1	1	100.00
V2		TOTAL			4	4	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	5.320s	274.813us	1	1	100.00
		keymgr_dpe_tl_intg_err	5.220s	243.141us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	3.320s	704.765us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	3.320s	704.765us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	3.320s	704.765us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	3.320s	704.765us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	5.310s	383.774us	1	1	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	5.320s	274.813us	1	1	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	5.320s	274.813us	1	1	100.00
V2S		TOTAL			4	4	100.00
		TOTAL			14	14	100.00