KMAC/UNMASKED Simulation Results

Thursday April 17 2025 17:08:19 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	17.710s	1.389ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.750s	23.518us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.810s	47.472us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.700s	1.127ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.250s	383.594us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.580s	41.509us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.810s	47.472us	1	1	100.00
		kmac_csr_aliasing	4.250s	383.594us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.510s	27.968us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.090s	99.922us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	25.614m	44.302ms	1	1	100.00
V2	burst_write	kmac_burst_write	10.554m	428.926ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	29.840s	3.692ms	1	1	100.00
		kmac_test_vectors_sha3_256	26.732m	92.100ms	1	1	100.00
		kmac_test_vectors_sha3_384	16.845m	92.022ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.140s	2.123ms	1	1	100.00
		kmac_test_vectors_shake_128	30.359m	296.356ms	1	1	100.00
		kmac_test_vectors_shake_256	22.391m	301.067ms	1	1	100.00
		kmac_test_vectors_kmac	3.360s	137.589us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.260s	54.896us	1	1	100.00
V2	sideload	kmac_sideload	46.880s	4.201ms	1	1	100.00
V2	app	kmac_app	40.570s	3.915ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.066m	16.296ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.826m	30.140ms	1	1	100.00
V2	error	kmac_error	49.660s	3.245ms	1	1	100.00
V2	key_error	kmac_key_error	6.120s	669.039us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.759m	10.025ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	16.020s	665.228us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	20.420s	4.557ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	3.030s	246.632us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.140s	80.315us	1	1	100.00
V2	stress_all	kmac_stress_all	41.749m	331.806ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.820s	29.528us	1	1	100.00
V2	alert_test	kmac_alert_test	1.610s	79.706us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.030s	402.393us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.030s	402.393us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.750s	23.518us	1	1	100.00
		kmac_csr_rw	1.810s	47.472us	1	1	100.00
		kmac_csr_aliasing	4.250s	383.594us	1	1	100.00
		kmac_same_csr_outstanding	2.870s	42.065us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.750s	23.518us	1	1	100.00
		kmac_csr_rw	1.810s	47.472us	1	1	100.00
		kmac_csr_aliasing	4.250s	383.594us	1	1	100.00
		kmac_same_csr_outstanding	2.870s	42.065us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.670s	116.088us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.670s	116.088us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.670s	116.088us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.670s	116.088us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.800s	95.260us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	23.600s	2.467ms	1	1	100.00
		kmac_tl_intg_err	3.780s	389.737us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.780s	389.737us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.140s	80.315us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	17.710s	1.389ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	46.880s	4.201ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.670s	116.088us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	23.600s	2.467ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	23.600s	2.467ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	23.600s	2.467ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	17.710s	1.389ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.140s	80.315us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	23.600s	2.467ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.163m	1.843ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	17.710s	1.389ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.478m	11.059ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.14550875704051391524331572966611773529555153793042567343278406618185725344767
      Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10025456252 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9fcae000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
        UVM_INFO @ 10025456252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.948056154968746075151427377976903016639079408667530656365225416987720402787
      Line 207, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11059074063 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 11059074063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---