91d1222| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 31.000s | 6.109ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 10.000s | 28.084us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 10.000s | 43.019us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 10.000s | 228.292us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 10.000s | 52.280us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 9.000s | 5.221us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 10.000s | 43.019us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 10.000s | 52.280us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 9.000s | 459.481us | 0 | 1 | 0.00 |
| mbx_stress_zero_delays | 13.000s | 1.410ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 14.000s | 1.904ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 4.000s | 44.135us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 11.000s | 4.376us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 11.000s | 4.376us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 10.000s | 28.084us | 1 | 1 | 100.00 |
| mbx_csr_rw | 10.000s | 43.019us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 10.000s | 52.280us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 10.000s | 59.616us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 10.000s | 28.084us | 1 | 1 | 100.00 |
| mbx_csr_rw | 10.000s | 43.019us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 10.000s | 52.280us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 10.000s | 59.616us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 4 | 6 | 66.67 | |||
| V2S | tl_intg_err | mbx_sec_cm | 4.000s | 12.856us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 11.000s | 6.219us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 10 | 14 | 71.43 |
xmsim: *E,ASRTST (/nightly/runs/scratch/master/mbx-sim-xcelium/default/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,286): Assertion ReadyAssertedWhenRead_A has failed has 1 failures:
0.mbx_stress.5886287989201142670203876915359788327844300213816179730814330154453049073860
Line 125, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/mbx-sim-xcelium/default/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,286): (time 459481191 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
UVM_ERROR @ 459481191 ps: (mbx_ombx.sv:286) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 459481191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Invalid, value: * a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.31249698930716864277641472117387408921480171788310250921810753502630388970757
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 4375672 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x63fb4728 a_data = 0x1e7ee54c a_mask = 0x0 a_size = 0x1 a_param = 0x0 a_source = 0xc2 a_opcode = Invalid, value: 3 a_user = 0x2682f d_data = 0x5ae90f5b d_size = 0x3 d_param = 0x0 d_source = 0x2e d_opcode = AccessAckData d_error = 0 d_user = 11111011100001 d_sink = 1 req_abort_after_a_valid_len = 1 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 4375672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.19032128795919843916133535814589951032757805895834399291172174238646826711977
Line 88, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 6219148 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xdb767f78 a_data = 0xc918886b a_mask = 0x3 a_size = 0x1 a_param = 0x0 a_source = 0xc3 a_opcode = Get a_user = 0x24c6d d_data = 0x4c34aaf4 d_size = 0x0 d_param = 0x0 d_source = 0x6a d_opcode = AccessAck d_error = 0 d_user = 11100000110000 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 6219148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.12930137262201225792096249459765662418722712638951894408784497374020006756617
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 5220783 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x6a4d2ce8 a_data = 0xa9600b72 a_mask = 0x3 a_size = 0x3 a_param = 0x0 a_source = 0xbf a_opcode = PutPartialData a_user = 0x27ae0 d_data = 0x67e847c2 d_size = 0x0 d_param = 0x0 d_source = 0x4e d_opcode = AccessAckData d_error = 0 d_user = 11110100011011 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 5220783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---