ROM_CTRL/32KB Simulation Results

Thursday April 17 2025 17:08:19 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.050s 142.981us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 4.840s 285.068us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.960s 173.548us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.110s 373.880us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 3.870s 209.547us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.230s 181.795us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.960s 173.548us 1 1 100.00
rom_ctrl_csr_aliasing 3.870s 209.547us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.280s 1.071ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.560s 298.033us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.940s 137.115us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 13.670s 781.167us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 8.230s 546.853us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.250s 557.377us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 4.890s 372.976us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 4.890s 372.976us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 4.840s 285.068us 1 1 100.00
rom_ctrl_csr_rw 4.960s 173.548us 1 1 100.00
rom_ctrl_csr_aliasing 3.870s 209.547us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.010s 170.017us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 4.840s 285.068us 1 1 100.00
rom_ctrl_csr_rw 4.960s 173.548us 1 1 100.00
rom_ctrl_csr_aliasing 3.870s 209.547us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.010s 170.017us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 54.630s 1.919ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 19.830s 1.627ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.944m 3.650ms 1 1 100.00
rom_ctrl_tl_intg_err 38.780s 1.018ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.944m 3.650ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.944m 3.650ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 54.630s 1.919ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 54.630s 1.919ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 54.630s 1.919ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 54.630s 1.919ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 54.630s 1.919ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.944m 3.650ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.944m 3.650ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.050s 142.981us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.050s 142.981us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.050s 142.981us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 38.780s 1.018ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 54.630s 1.919ms 1 1 100.00
rom_ctrl_kmac_err_chk 8.230s 546.853us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 54.630s 1.919ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 54.630s 1.919ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 54.630s 1.919ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 19.830s 1.627ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.944m 3.650ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 3.934m 3.211ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00