ROM_CTRL/64KB Simulation Results

Thursday April 17 2025 17:08:19 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 10.990s 4.155ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.260s 236.685us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.340s 628.344us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.690s 211.965us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 8.190s 216.670us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 9.520s 307.815us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.340s 628.344us 1 1 100.00
rom_ctrl_csr_aliasing 8.190s 216.670us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.140s 375.515us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.020s 1.411ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.660s 3.662ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 29.920s 2.153ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.960s 1.369ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.860s 1.483ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 10.060s 1.032ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 10.060s 1.032ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.260s 236.685us 1 1 100.00
rom_ctrl_csr_rw 6.340s 628.344us 1 1 100.00
rom_ctrl_csr_aliasing 8.190s 216.670us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.560s 709.367us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.260s 236.685us 1 1 100.00
rom_ctrl_csr_rw 6.340s 628.344us 1 1 100.00
rom_ctrl_csr_aliasing 8.190s 216.670us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.560s 709.367us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.077m 7.161ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 27.660s 3.458ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.718m 1.427ms 1 1 100.00
rom_ctrl_tl_intg_err 37.820s 801.260us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.718m 1.427ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.718m 1.427ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.077m 7.161ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.077m 7.161ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.077m 7.161ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.077m 7.161ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.077m 7.161ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.718m 1.427ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.718m 1.427ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 10.990s 4.155ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 10.990s 4.155ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 10.990s 4.155ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 37.820s 801.260us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.077m 7.161ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.960s 1.369ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.077m 7.161ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.077m 7.161ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.077m 7.161ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 27.660s 3.458ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.718m 1.427ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.085m 4.452ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00