SPI_DEVICE/1R1W Simulation Results

Thursday April 17 2025 17:08:19 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.047m	22.953ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.810s	136.204us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.910s	64.466us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.510s	187.453us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.450s	915.525us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.420s	194.039us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.910s	64.466us	1	1	100.00
		spi_device_csr_aliasing	17.450s	915.525us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.550s	93.487us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.640s	70.666us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.970s	20.970us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.860s	22.885us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.600s	1.597us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	6.510s	780.338us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	6.510s	780.338us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	12.220s	4.943ms	1	1	100.00
		spi_device_tpm_sts_read	1.840s	21.055us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	13.850s	3.389ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.160s	5.050ms	1	1	100.00
		spi_device_flash_all	1.960s	49.439us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	13.780s	41.286ms	1	1	100.00
		spi_device_flash_all	1.960s	49.439us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	13.780s	41.286ms	1	1	100.00
		spi_device_flash_all	1.960s	49.439us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.960s	49.439us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	9.690s	2.671ms	1	1	100.00
		spi_device_flash_all	1.960s	49.439us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	9.690s	2.671ms	1	1	100.00
		spi_device_flash_all	1.960s	49.439us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	9.690s	2.671ms	1	1	100.00
		spi_device_flash_all	1.960s	49.439us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	9.690s	2.671ms	1	1	100.00
		spi_device_flash_all	1.960s	49.439us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	9.690s	2.671ms	1	1	100.00
		spi_device_flash_all	1.960s	49.439us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	5.070s	464.573us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	5.140s	208.345us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	5.140s	208.345us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	5.140s	208.345us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	20.000s	1.476ms	1	1	100.00
		spi_device_read_buffer_direct	4.450s	1.175ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	5.140s	208.345us	1	1	100.00
		spi_device_flash_all	1.960s	49.439us	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.960s	49.439us	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.960s	49.439us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.060s	1.370ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.060s	1.370ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.047m	22.953ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	3.057m	34.305ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.150s	39.264us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.860s	54.718us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.660s	50.042us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.030s	117.861us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.030s	117.861us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.810s	136.204us	1	1	100.00
		spi_device_csr_rw	1.910s	64.466us	1	1	100.00
		spi_device_csr_aliasing	17.450s	915.525us	1	1	100.00
		spi_device_same_csr_outstanding	2.740s	51.349us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.810s	136.204us	1	1	100.00
		spi_device_csr_rw	1.910s	64.466us	1	1	100.00
		spi_device_csr_aliasing	17.450s	915.525us	1	1	100.00
		spi_device_same_csr_outstanding	2.740s	51.349us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.180s	1.064ms	1	1	100.00
		spi_device_tl_intg_err	6.440s	287.626us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.440s	287.626us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.014m	19.132ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.89840401777839897899105739897092986256826381577415519635775639922860987945392
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @  19884638 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[76])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @  19884638 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @  19884638 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[972])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.83458773476886924468927692451691172691249010227707025690216041156872569914575
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1072829 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1072829 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1092829 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcb754e [110010110111010101001110] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1092829 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0xcb754e [110010110111010101001110] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])