SPI_HOST Simulation Results

Thursday April 17 2025 17:08:19 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.350m	15.244ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	46.136us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	26.701us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	204.460us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	57.395us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	23.068us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	26.701us	1	1	100.00
		spi_host_csr_aliasing	4.000s	57.395us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	22.653us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	28.132us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	101.226us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	14.000s	1.006ms	1	1	100.00
		spi_host_error_cmd	4.000s	50.890us	1	1	100.00
		spi_host_event	14.000s	5.954ms	1	1	100.00
V2	clock_rate	spi_host_speed	5.000s	453.544us	1	1	100.00
V2	speed	spi_host_speed	5.000s	453.544us	1	1	100.00
V2	chip_select_timing	spi_host_speed	5.000s	453.544us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	8.000s	275.182us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	633.346us	1	1	100.00
V2	cpol_cpha	spi_host_speed	5.000s	453.544us	1	1	100.00
V2	full_cycle	spi_host_speed	5.000s	453.544us	1	1	100.00
V2	duplex	spi_host_smoke	1.350m	15.244ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	1.350m	15.244ms	1	1	100.00
V2	stress_all	spi_host_stress_all	5.000s	45.571us	1	1	100.00
V2	spien	spi_host_spien	7.000s	1.891ms	1	1	100.00
V2	stall	spi_host_status_stall	17.000s	1.792ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	936.143us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	14.000s	1.006ms	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	28.866us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	31.859us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	100.819us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	100.819us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	46.136us	1	1	100.00
		spi_host_csr_rw	4.000s	26.701us	1	1	100.00
		spi_host_csr_aliasing	4.000s	57.395us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	52.142us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	46.136us	1	1	100.00
		spi_host_csr_rw	4.000s	26.701us	1	1	100.00
		spi_host_csr_aliasing	4.000s	57.395us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	52.142us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	82.906us	1	1	100.00
		spi_host_sec_cm	4.000s	74.054us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	82.906us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	27.817m	158.307ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.68162341257921318356806134072365893926143048485065761659246890137435286334547
      Line 190, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 158306879205 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1c318314, Comparison=CompareOpEq, exp_data=0x0, call_count=22)
        UVM_INFO @ 158306879205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---